disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/armada/armada_510.c
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..
@@ -1,31 +1,72 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2012 Russell King
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Armada 510 (aka Dove) variant support
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  */
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 #include <linux/clk.h>
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 #include <linux/io.h>
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-#include <drm/drm_crtc_helper.h>
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+#include <drm/drm_probe_helper.h>
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 #include "armada_crtc.h"
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 #include "armada_drm.h"
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 #include "armada_hw.h"
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13
 
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+struct armada510_variant_data {
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+	struct clk *clks[4];
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+	struct clk *sel_clk;
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+};
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+
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 static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
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 {
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+	struct armada510_variant_data *v;
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 	struct clk *clk;
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+	int idx;
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-	clk = devm_clk_get(dev, "ext_ref_clk1");
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-	if (IS_ERR(clk))
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-		return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk);
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+	v = devm_kzalloc(dev, sizeof(*v), GFP_KERNEL);
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+	if (!v)
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+		return -ENOMEM;
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-	dcrtc->extclk[0] = clk;
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+	dcrtc->variant_data = v;
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-	/* Lower the watermark so to eliminate jitter at higher bandwidths */
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-	armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
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+	if (dev->of_node) {
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+		struct property *prop;
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+		const char *s;
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+
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+		of_property_for_each_string(dev->of_node, "clock-names", prop,
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+					    s) {
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+			if (!strcmp(s, "ext_ref_clk0"))
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+				idx = 0;
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+			else if (!strcmp(s, "ext_ref_clk1"))
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+				idx = 1;
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+			else if (!strcmp(s, "plldivider"))
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+				idx = 2;
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+			else if (!strcmp(s, "axibus"))
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+				idx = 3;
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+			else
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+				continue;
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+
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+			clk = devm_clk_get(dev, s);
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+			if (IS_ERR(clk))
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+				return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :
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+					PTR_ERR(clk);
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+			v->clks[idx] = clk;
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+		}
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+	} else {
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+		clk = devm_clk_get(dev, "ext_ref_clk1");
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+		if (IS_ERR(clk))
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+			return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :
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+				PTR_ERR(clk);
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+
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+		v->clks[1] = clk;
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+	}
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+
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+	/*
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+	 * Lower the watermark so to eliminate jitter at higher bandwidths.
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+	 * Disable SRAM read wait state to avoid system hang with external
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+	 * clock.
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+	 */
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+	armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK,
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+		       dcrtc->base + LCD_CFG_RDREG4F);
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70
 
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 	/* Initialise SPU register */
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 	writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
..
..
@@ -34,65 +75,77 @@
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 	return 0;
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 }
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77
 
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+static const u32 armada510_clk_sels[] = {
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+	SCLK_510_EXTCLK0,
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+	SCLK_510_EXTCLK1,
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+	SCLK_510_PLL,
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+	SCLK_510_AXI,
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+};
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+
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+static const struct armada_clocking_params armada510_clocking = {
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+	/* HDMI requires -0.6%..+0.5% */
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+	.permillage_min = 994,
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+	.permillage_max = 1005,
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+	.settable = BIT(0) | BIT(1),
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+	.div_max = SCLK_510_INT_DIV_MASK,
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+};
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+
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 /*
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  * Armada510 specific SCLK register selection.
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  * This gets called with sclk = NULL to test whether the mode is
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  * supportable, and again with sclk != NULL to set the clocks up for
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  * that.  The former can return an error, but the latter is expected
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  * not to.
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- *
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- * We currently are pretty rudimentary here, always selecting
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- * EXT_REF_CLK_1 for LCD0 and erroring LCD1.  This needs improvement!
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  */
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 static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
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 	const struct drm_display_mode *mode, uint32_t *sclk)
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 {
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-	struct clk *clk = dcrtc->extclk[0];
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-	int ret;
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+	struct armada510_variant_data *v = dcrtc->variant_data;
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+	unsigned long desired_khz = mode->crtc_clock;
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+	struct armada_clk_result res;
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+	int ret, idx;
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-	if (dcrtc->num == 1)
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-		return -EINVAL;
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+	idx = armada_crtc_select_clock(dcrtc, &res, &armada510_clocking,
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+				       v->clks, ARRAY_SIZE(v->clks),
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+				       desired_khz);
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+	if (idx < 0)
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+		return idx;
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113
 
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-	if (IS_ERR(clk))
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-		return PTR_ERR(clk);
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-
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-	if (dcrtc->clk != clk) {
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-		ret = clk_prepare_enable(clk);
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-		if (ret)
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-			return ret;
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-		dcrtc->clk = clk;
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-	}
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+	ret = clk_prepare_enable(res.clk);
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+	if (ret)
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+		return ret;
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 	if (sclk) {
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-		uint32_t rate, ref, div;
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+		clk_set_rate(res.clk, res.desired_clk_hz);
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120
 
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-		rate = mode->clock * 1000;
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-		ref = clk_round_rate(clk, rate);
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-		div = DIV_ROUND_UP(ref, rate);
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-		if (div < 1)
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-			div = 1;
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+		*sclk = res.div | armada510_clk_sels[idx];
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122
 
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-		clk_set_rate(clk, ref);
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-		*sclk = div | SCLK_510_EXTCLK1;
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+		/* We are now using this clock */
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+		v->sel_clk = res.clk;
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+		swap(dcrtc->clk, res.clk);
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 	}
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+
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+	clk_disable_unprepare(res.clk);
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129
 
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 	return 0;
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 }
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132
 
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 static void armada510_crtc_disable(struct armada_crtc *dcrtc)
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 {
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-	if (!IS_ERR(dcrtc->clk)) {
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+	if (dcrtc->clk) {
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 		clk_disable_unprepare(dcrtc->clk);
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-		dcrtc->clk = ERR_PTR(-EINVAL);
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+		dcrtc->clk = NULL;
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 	}
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 }
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 static void armada510_crtc_enable(struct armada_crtc *dcrtc,
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 	const struct drm_display_mode *mode)
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 {
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-	if (IS_ERR(dcrtc->clk)) {
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-		dcrtc->clk = dcrtc->extclk[0];
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-		WARN_ON(clk_prepare_enable(dcrtc->clk));
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+	struct armada510_variant_data *v = dcrtc->variant_data;
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+
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+	if (!dcrtc->clk && v->sel_clk) {
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+		if (!WARN_ON(clk_prepare_enable(v->sel_clk)))
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+			dcrtc->clk = v->sel_clk;
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 	}
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 }
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