disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/arm/malidp_regs.h
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@@ -1,11 +1,7 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
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  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
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- *
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- * This program is free software and is provided to you under the terms of the
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- * GNU General Public License version 2 as published by the Free Software
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- * Foundation, and any use by you of this program is subject to the terms
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- * of such GNU licence.
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  *
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  * ARM Mali DP500/DP550/DP650 registers definition.
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  */
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@@ -198,10 +194,13 @@
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 #define MALIDP500_LV_YUV2RGB		((s16)(-0xB8))
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 #define MALIDP500_DE_LV_BASE		0x00100
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 #define MALIDP500_DE_LV_PTR_BASE	0x00124
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+#define MALIDP500_DE_LV_AD_CTRL		0x00400
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 #define MALIDP500_DE_LG1_BASE		0x00200
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 #define MALIDP500_DE_LG1_PTR_BASE	0x0021c
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+#define MALIDP500_DE_LG1_AD_CTRL	0x0040c
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 #define MALIDP500_DE_LG2_BASE		0x00300
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 #define MALIDP500_DE_LG2_PTR_BASE	0x0031c
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+#define MALIDP500_DE_LG2_AD_CTRL	0x00418
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 #define MALIDP500_SE_BASE		0x00c00
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 #define MALIDP500_SE_CONTROL		0x00c0c
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 #define MALIDP500_SE_MEMWRITE_OUT_SIZE	0x00c2c
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@@ -210,6 +209,16 @@
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 #define MALIDP500_DC_IRQ_BASE		0x00f00
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 #define MALIDP500_CONFIG_VALID		0x00f00
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 #define MALIDP500_CONFIG_ID		0x00fd4
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+
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+/*
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+ * The quality of service (QoS) register on the DP500. RQOS register values
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+ * are driven by the ARQOS signal, using AXI transacations, dependent on the
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+ * FIFO input level.
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+ * The RQOS register can also set QoS levels for:
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+ *    - RED_ARQOS   @ A 4-bit signal value for close to underflow conditions
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+ *    - GREEN_ARQOS @ A 4-bit signal value for normal conditions
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+ */
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+#define MALIDP500_RQOS_QUALITY          0x00500
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 /* register offsets and bits specific to DP550/DP650 */
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 #define MALIDP550_ADDR_SPACE_SIZE	0x10000
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@@ -228,10 +237,13 @@
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 #define MALIDP550_LV_YUV2RGB		0x00084
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 #define MALIDP550_DE_LV1_BASE		0x00100
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 #define MALIDP550_DE_LV1_PTR_BASE	0x00124
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+#define MALIDP550_DE_LV1_AD_CTRL	0x001B8
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 #define MALIDP550_DE_LV2_BASE		0x00200
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 #define MALIDP550_DE_LV2_PTR_BASE	0x00224
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+#define MALIDP550_DE_LV2_AD_CTRL	0x002B8
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 #define MALIDP550_DE_LG_BASE		0x00300
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 #define MALIDP550_DE_LG_PTR_BASE	0x0031c
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+#define MALIDP550_DE_LG_AD_CTRL		0x00330
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 #define MALIDP550_DE_LS_BASE		0x00400
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 #define MALIDP550_DE_LS_PTR_BASE	0x0042c
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 #define MALIDP550_DE_PERF_BASE		0x00500
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@@ -247,6 +259,31 @@
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 #define MALIDP550_CONFIG_VALID		0x0c014
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 #define MALIDP550_CONFIG_ID		0x0ffd4
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+/* register offsets specific to DP650 */
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+#define MALIDP650_DE_LV_MMU_CTRL	0x000D0
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+#define MALIDP650_DE_LG_MMU_CTRL	0x00048
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+#define MALIDP650_DE_LS_MMU_CTRL	0x00078
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+
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+/* bit masks to set the MMU control register */
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+#define MALIDP_MMU_CTRL_EN		(1 << 0)
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+#define MALIDP_MMU_CTRL_MODE		(1 << 4)
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+#define MALIDP_MMU_CTRL_PX_PS(x)	(1 << (8 + (x)))
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+#define MALIDP_MMU_CTRL_PP_NUM_REQ(x)	(((x) & 0x7f) << 12)
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+
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+/* AFBC register offsets relative to MALIDPXXX_DE_LX_AD_CTRL */
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+/* The following register offsets are common for DP500, DP550 and DP650 */
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+#define MALIDP_AD_CROP_H                0x4
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+#define MALIDP_AD_CROP_V                0x8
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+#define MALIDP_AD_END_PTR_LOW           0xc
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+#define MALIDP_AD_END_PTR_HIGH          0x10
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+
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+/* AFBC decoder Registers */
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+#define MALIDP_AD_EN                    BIT(0)
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+#define MALIDP_AD_YTR                   BIT(4)
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+#define MALIDP_AD_BS                    BIT(8)
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+#define MALIDP_AD_CROP_RIGHT_OFFSET     16
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+#define MALIDP_AD_CROP_BOTTOM_OFFSET    16
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+
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 /*
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  * Starting with DP550 the register map blocks has been standardised to the
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  * following layout: