~hc/RK356X_SDK_RELEASE.git

..	..	@@ -87,6 +87,26 @@
87	87	//CC_UVD_HARVESTING
88	88	#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1
89	89	#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L
	90	+//UVD_DPG_LMA_CTL
	91	+#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0
	92	+#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1
	93	+#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2
	94	+#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4
	95	+#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10
	96	+#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L
	97	+#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L
	98	+#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L
	99	+#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L
	100	+#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L
	101	+//UVD_DPG_PAUSE
	102	+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0
	103	+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1
	104	+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2
	105	+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3
	106	+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L
	107	+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L
	108	+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L
	109	+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L
90	110	//UVD_SCRATCH1
91	111	#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0
92	112	#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL
..	..	@@ -292,6 +312,11 @@
292	312	//UVD_GPCOM_VCPU_DATA1
293	313	#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
294	314	#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL
	315	+//UVD_ENGINE_CNTL
	316	+#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
	317	+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
	318	+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
	319	+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
295	320	//UVD_UDEC_DBW_UV_ADDR_CONFIG
296	321	#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
297	322	#define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
..	..	@@ -965,6 +990,7 @@
965	990	#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
966	991	#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
967	992	#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
	993	+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
968	994	#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
969	995	#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
970	996	#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
..	..	@@ -973,6 +999,7 @@
973	999	#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
974	1000	#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
975	1001	#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
	1002	+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L
976	1003	//UVD_MASTINT_EN
977	1004	#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
978	1005	#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
..	..	@@ -982,6 +1009,9 @@
982	1009	#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
983	1010	#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
984	1011	#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L
	1012	+//UVD_SYS_INT_EN
	1013	+#define UVD_SYS_INT_EN__UVD_JRBC_EN__SHIFT 0x4
	1014	+#define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK 0x00000010L
985	1015	//JPEG_CGC_CTRL
986	1016	#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
987	1017	#define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
..	..	@@ -1022,6 +1052,19 @@
1022	1052	#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
1023	1053	#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
1024	1054	#define UVD_LMI_CTRL__RFU_MASK 0xF8000000L
	1055	+//UVD_LMI_STATUS
	1056	+#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
	1057	+#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
	1058	+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
	1059	+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
	1060	+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
	1061	+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
	1062	+#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
	1063	+#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
	1064	+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
	1065	+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
	1066	+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
	1067	+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
1025	1068	//UVD_LMI_SWAP_CNTL
1026	1069	#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
1027	1070	#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
..	..	@@ -1055,6 +1098,9 @@
1055	1098	#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
1056	1099	#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
1057	1100	#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
	1101	+//UVD_MPC_CNTL
	1102	+#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
	1103	+#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
1058	1104	//UVD_MPC_SET_MUXA0
1059	1105	#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
1060	1106	#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
..	..	@@ -1136,7 +1182,11 @@
1136	1182	#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL
1137	1183	//UVD_VCPU_CNTL
1138	1184	#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
	1185	+#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
	1186	+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
1139	1187	#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
	1188	+#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L
	1189	+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L
1140	1190	//UVD_SOFT_RESET
1141	1191	#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
1142	1192	#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1