disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
..
..
@@ -33,6 +33,14 @@
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 #define mmUVD_POWER_STATUS_BASE_IDX                                                                    1
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 #define mmCC_UVD_HARVESTING                                                                            0x00c7
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 #define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1
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+#define mmUVD_DPG_LMA_CTL                                                                              0x00d1
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+#define mmUVD_DPG_LMA_CTL_BASE_IDX                                                                     1
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+#define mmUVD_DPG_LMA_DATA                                                                             0x00d2
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+#define mmUVD_DPG_LMA_DATA_BASE_IDX                                                                    1
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+#define mmUVD_DPG_LMA_MASK                                                                             0x00d3
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+#define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1
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+#define mmUVD_DPG_PAUSE                                                                                0x00d4
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+#define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1
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 #define mmUVD_SCRATCH1                                                                                 0x00d5
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 #define mmUVD_SCRATCH1_BASE_IDX                                                                        1
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 #define mmUVD_SCRATCH2                                                                                 0x00d6
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@@ -74,6 +82,18 @@
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 #define mmUVD_LCM_CGC_CNTRL                                                                            0x0123
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 #define mmUVD_LCM_CGC_CNTRL_BASE_IDX                                                                   1
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+#define mmUVD_MIF_CURR_UV_ADDR_CONFIG                                                                  0x0184
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+#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX                                                         1
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+#define mmUVD_MIF_REF_UV_ADDR_CONFIG                                                                   0x0185
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+#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX                                                          1
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+#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG                                                                0x0186
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+#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX                                                       1
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+#define mmUVD_MIF_CURR_ADDR_CONFIG                                                                     0x0192
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+#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX                                                            1
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+#define mmUVD_MIF_REF_ADDR_CONFIG                                                                      0x0193
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+#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX                                                             1
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+#define mmUVD_MIF_RECON1_ADDR_CONFIG                                                                   0x01c5
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+#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX                                                          1
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 // addressBlock: uvd_uvdnpdec
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 // base address: 0x20000
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@@ -121,6 +141,8 @@
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 #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX                                                                1
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 #define mmUVD_GPCOM_VCPU_DATA1                                                                         0x03c5
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 #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX                                                                1
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+#define mmUVD_ENGINE_CNTL                                                                              0x03c6
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+#define mmUVD_ENGINE_CNTL_BASE_IDX                                                                     1
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 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG                                                                  0x03d2
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 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX                                                         1
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 #define mmUVD_UDEC_ADDR_CONFIG                                                                         0x03d3
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@@ -307,6 +329,8 @@
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 #define mmUVD_LMI_CTRL2_BASE_IDX                                                                       1
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 #define mmUVD_MASTINT_EN                                                                               0x0540
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 #define mmUVD_MASTINT_EN_BASE_IDX                                                                      1
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+#define mmUVD_SYS_INT_EN                                                                               0x0541
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+#define mmUVD_SYS_INT_EN_BASE_IDX                                                                      1
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 #define mmJPEG_CGC_CTRL                                                                                0x0565
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 #define mmJPEG_CGC_CTRL_BASE_IDX                                                                       1
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 #define mmUVD_LMI_CTRL                                                                                 0x0566
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@@ -317,6 +341,8 @@
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 #define mmUVD_LMI_VM_CTRL_BASE_IDX                                                                     1
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 #define mmUVD_LMI_SWAP_CNTL                                                                            0x056d
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 #define mmUVD_LMI_SWAP_CNTL_BASE_IDX                                                                   1
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+#define mmUVD_MPC_CNTL                                                                                 0x0577
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+#define mmUVD_MPC_CNTL_BASE_IDX                                                                        1
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 #define mmUVD_MPC_SET_MUXA0                                                                            0x0579
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 #define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1
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 #define mmUVD_MPC_SET_MUXA1                                                                            0x057a