kernel/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
.. .. @@ -220,6 +220,8 @@ 220 220 #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 221 221 #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff 222 222 #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 223 +#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2224 +#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1223 225 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 224 226 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 225 227 #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2