forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
....@@ -4444,14 +4444,90 @@
44444444 
44454445 /* Registers that spilled out of sid.h */
44464446 #define mmDATA_FORMAT                              0x1AC0
4447
+#define mmLB0_DATA_FORMAT                               0x1AC0
4448
+#define mmLB1_DATA_FORMAT                               0x1DC0
4449
+#define mmLB2_DATA_FORMAT                               0x40C0
4450
+#define mmLB3_DATA_FORMAT                               0x43C0
4451
+#define mmLB4_DATA_FORMAT                               0x46C0
4452
+#define mmLB5_DATA_FORMAT                               0x49C0
44474453 #define mmDESKTOP_HEIGHT                           0x1AC1
4454
+#define mmLB0_DESKTOP_HEIGHT                            0x1AC1
4455
+#define mmLB1_DESKTOP_HEIGHT                            0x1DC1
4456
+#define mmLB2_DESKTOP_HEIGHT                            0x40C1
4457
+#define mmLB3_DESKTOP_HEIGHT                            0x43C1
4458
+#define mmLB4_DESKTOP_HEIGHT                            0x46C1
4459
+#define mmLB5_DESKTOP_HEIGHT                            0x49C1
44484460 #define mmDC_LB_MEMORY_SPLIT                       0x1AC3
4461
+#define mmLB0_DC_LB_MEMORY_SPLIT                        0x1AC3
4462
+#define mmLB1_DC_LB_MEMORY_SPLIT                        0x1DC3
4463
+#define mmLB2_DC_LB_MEMORY_SPLIT                        0x40C3
4464
+#define mmLB3_DC_LB_MEMORY_SPLIT                        0x43C3
4465
+#define mmLB4_DC_LB_MEMORY_SPLIT                        0x46C3
4466
+#define mmLB5_DC_LB_MEMORY_SPLIT                        0x49C3
4467
+#define mmDC_LB_MEM_SIZE                                0x1AC4
4468
+#define mmLB0_DC_LB_MEM_SIZE                            0x1AC4
4469
+#define mmLB1_DC_LB_MEM_SIZE                            0x1DC4
4470
+#define mmLB2_DC_LB_MEM_SIZE                            0x40C4
4471
+#define mmLB3_DC_LB_MEM_SIZE                            0x43C4
4472
+#define mmLB4_DC_LB_MEM_SIZE                            0x46C4
4473
+#define mmLB5_DC_LB_MEM_SIZE                            0x49C4
44494474 #define mmPRIORITY_A_CNT                           0x1AC6
4475
+#define mmLB0_PRIORITY_A_CNT                            0x1AC6
4476
+#define mmLB1_PRIORITY_A_CNT                            0x1DC6
4477
+#define mmLB2_PRIORITY_A_CNT                            0x40C6
4478
+#define mmLB3_PRIORITY_A_CNT                            0x43C6
4479
+#define mmLB4_PRIORITY_A_CNT                            0x46C6
4480
+#define mmLB5_PRIORITY_A_CNT                            0x49C6
44504481 #define mmPRIORITY_B_CNT                           0x1AC7
4482
+#define mmLB0_PRIORITY_B_CNT                            0x1AC7
4483
+#define mmLB1_PRIORITY_B_CNT                            0x1DC7
4484
+#define mmLB2_PRIORITY_B_CNT                            0x40C7
4485
+#define mmLB3_PRIORITY_B_CNT                            0x43C7
4486
+#define mmLB4_PRIORITY_B_CNT                            0x46C7
4487
+#define mmLB5_PRIORITY_B_CNT                            0x49C7
44514488 #define mmDPG_PIPE_ARBITRATION_CONTROL3            0x1B32
4489
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3        0x1B32
4490
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3        0x1E32
4491
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3        0x4132
4492
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3        0x4432
4493
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3        0x4732
4494
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3        0x4A32
44524495 #define mmINT_MASK                                 0x1AD0
4496
+#define mmLB0_INT_MASK                                  0x1AD0
4497
+#define mmLB1_INT_MASK                                  0x1DD0
4498
+#define mmLB2_INT_MASK                                  0x40D0
4499
+#define mmLB3_INT_MASK                                  0x43D0
4500
+#define mmLB4_INT_MASK                                  0x46D0
4501
+#define mmLB5_INT_MASK                                  0x49D0
44534502 #define mmVLINE_STATUS                             0x1AEE
4503
+#define mmLB0_VLINE_STATUS                              0x1AEE
4504
+#define mmLB1_VLINE_STATUS                              0x1DEE
4505
+#define mmLB2_VLINE_STATUS                              0x40EE
4506
+#define mmLB3_VLINE_STATUS                              0x43EE
4507
+#define mmLB4_VLINE_STATUS                              0x46EE
4508
+#define mmLB5_VLINE_STATUS                              0x49EE
44544509 #define mmVBLANK_STATUS                            0x1AEF
4510
+#define mmLB0_VBLANK_STATUS                             0x1AEF
4511
+#define mmLB1_VBLANK_STATUS                             0x1DEF
4512
+#define mmLB2_VBLANK_STATUS                             0x40EF
4513
+#define mmLB3_VBLANK_STATUS                             0x43EF
4514
+#define mmLB4_VBLANK_STATUS                             0x46EF
4515
+#define mmLB5_VBLANK_STATUS                             0x49EF
44554516 
4517
+#define mmSCL_HORZ_FILTER_INIT_RGB_LUMA            0x1B4C
4518
+#define mmSCL0_SCL_HORZ_FILTER_INIT_RGB_LUMA            0x1B4C
4519
+#define mmSCL1_SCL_HORZ_FILTER_INIT_RGB_LUMA            0x1E4C
4520
+#define mmSCL2_SCL_HORZ_FILTER_INIT_RGB_LUMA            0x414C
4521
+#define mmSCL3_SCL_HORZ_FILTER_INIT_RGB_LUMA            0x444C
4522
+#define mmSCL4_SCL_HORZ_FILTER_INIT_RGB_LUMA            0x474C
4523
+#define mmSCL5_SCL_HORZ_FILTER_INIT_RGB_LUMA            0x4A4C
4524
+
4525
+#define mmSCL_HORZ_FILTER_INIT_CHROMA              0x1B4D
4526
+#define mmSCL0_SCL_HORZ_FILTER_INIT_CHROMA              0x1B4D
4527
+#define mmSCL1_SCL_HORZ_FILTER_INIT_CHROMA              0x1E4D
4528
+#define mmSCL2_SCL_HORZ_FILTER_INIT_CHROMA              0x414D
4529
+#define mmSCL3_SCL_HORZ_FILTER_INIT_CHROMA              0x444D
4530
+#define mmSCL4_SCL_HORZ_FILTER_INIT_CHROMA              0x474D
4531
+#define mmSCL5_SCL_HORZ_FILTER_INIT_CHROMA              0x4A4D
44564532 
44574533 #endif