disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
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@@ -52,7 +52,7 @@
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 /* macro to set register fields. */
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 #define REG_SET_N(reg_name, n, initial_val, ...)	\
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-		generic_reg_update_ex(CTX, \
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+		generic_reg_set_ex(CTX, \
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 				REG(reg_name), \
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 				initial_val, \
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 				n, __VA_ARGS__)
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@@ -225,7 +225,6 @@
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 #define REG_UPDATE_N(reg_name, n, ...)	\
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 		generic_reg_update_ex(CTX, \
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 				REG(reg_name), \
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-				REG_READ(reg_name), \
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 				n, __VA_ARGS__)
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 #define REG_UPDATE(reg_name, field, val)	\
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@@ -380,16 +379,11 @@
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 /* macro to update a register field to specified values in given sequences.
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  * useful when toggling bits
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  */
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-#define REG_UPDATE_SEQ(reg, field, value1, value2) \
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-{	uint32_t val = REG_UPDATE(reg, field, value1); \
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-	REG_SET(reg, val, field, value2); }
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-
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-/* macro to update fields in register 1 field at a time in given order */
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-#define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \
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+#define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) \
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 {	uint32_t val = REG_UPDATE(reg, f1, v1); \
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 	REG_SET(reg, val, f2, v2); }
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-#define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \
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+#define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \
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 {	uint32_t val = REG_UPDATE(reg, f1, v1); \
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 	val = REG_SET(reg, val, f2, v2); \
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 	REG_SET(reg, val, f3, v3); }
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@@ -464,7 +458,14 @@
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 #define IX_REG_READ(index_reg_name, data_reg_name, index) \
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 		generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index))
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+#define IX_REG_GET_N(index_reg_name, data_reg_name, index, n, ...) \
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+		generic_indirect_reg_get(CTX, REG(index_reg_name), REG(data_reg_name), \
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+				IND_REG(index), \
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+				n, __VA_ARGS__)
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+#define IX_REG_GET(index_reg_name, data_reg_name, index, field, val) \
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+		IX_REG_GET_N(index_reg_name, data_reg_name, index, 1, \
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+				FN(data_reg_name, field), val)
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 #define IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, n, ...)	\
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 		generic_indirect_reg_update_ex(CTX, \
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@@ -485,10 +486,35 @@
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 		uint32_t addr_index, uint32_t addr_data,
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 		uint32_t index);
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+uint32_t generic_indirect_reg_get(const struct dc_context *ctx,
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+		uint32_t addr_index, uint32_t addr_data,
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+		uint32_t index, int n,
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+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
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+		...);
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+
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 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
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 		uint32_t addr_index, uint32_t addr_data,
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 		uint32_t index, uint32_t reg_val, int n,
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 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
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 		...);
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+/* register offload macros
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+ *
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+ * instead of MMIO to register directly, in some cases we want
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+ * to gather register sequence and execute the register sequence
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+ * from another thread so we optimize time required for lengthy ops
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+ */
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+
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+/* start gathering register sequence */
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+#define REG_SEQ_START() \
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+	reg_sequence_start_gather(CTX)
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+
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+/* start execution of register sequence gathered since REG_SEQ_START */
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+#define REG_SEQ_SUBMIT() \
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+	reg_sequence_start_execute(CTX)
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+
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+/* wait for the last REG_SEQ_SUBMIT to finish */
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+#define REG_SEQ_WAIT_DONE() \
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+	reg_sequence_wait_done(CTX)
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+
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 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */