disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
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@@ -31,8 +31,8 @@
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 #define __DCN_CALCS_H__
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 #include "bw_fixed.h"
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-#include "display_clock.h"
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 #include "../dml/display_mode_lib.h"
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+
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 struct dc;
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 struct dc_state;
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@@ -504,10 +504,10 @@
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 	float prefetch_mode;
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 	float dstx_after_scaler;
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 	float dsty_after_scaler;
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-	float v_update_offset_pix;
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+	float v_update_offset_pix[number_of_planes_minus_one + 1];
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 	float total_repeater_delay_time;
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-	float v_update_width_pix;
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-	float v_ready_offset_pix;
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+	float v_update_width_pix[number_of_planes_minus_one + 1];
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+	float v_ready_offset_pix[number_of_planes_minus_one + 1];
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 	float t_setup;
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 	float t_wait;
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 	float bandwidth_available_for_immediate_flip;
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@@ -621,7 +621,8 @@
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 bool dcn_validate_bandwidth(
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 		struct dc *dc,
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-		struct dc_state *context);
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+		struct dc_state *context,
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+		bool fast_validate);
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 unsigned int dcn_find_dcfclk_suits_all(
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 	const struct dc *dc,
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@@ -631,5 +632,7 @@
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 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);
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 void dcn_bw_sync_calcs_and_dml(struct dc *dc);
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+enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode);
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+
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 #endif /* __DCN_CALCS_H__ */
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