disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
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@@ -48,6 +48,12 @@
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 	DDC_GPIO_REG_LIST(cd,id),\
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 	.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
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+	#define DDC_REG_LIST_DCN2(cd, id) \
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+	DDC_GPIO_REG_LIST(cd, id),\
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+	.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
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+	.phy_aux_cntl = REG(PHY_AUX_CNTL), \
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+	.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
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+
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 #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
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 	.type ## _reg =   REG(DC_GPIO_DDCVGA_ ## type),\
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 	.type ## _mask =  DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
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@@ -82,6 +88,11 @@
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 	DDC_GPIO_I2C_REG_LIST(cd),\
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 	.ddc_setup = 0
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+#define DDC_I2C_REG_LIST_DCN2(cd) \
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+	DDC_GPIO_I2C_REG_LIST(cd),\
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+	.ddc_setup = 0,\
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+	.phy_aux_cntl = REG(PHY_AUX_CNTL), \
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+	.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
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 #define DDC_MASK_SH_LIST_COMMON(mask_sh) \
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 		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
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 		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
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@@ -95,10 +106,18 @@
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 		SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
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 		SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
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+#define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \
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+	{DDC_MASK_SH_LIST_COMMON(mask_sh),\
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+	0,\
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+	0,\
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+	(PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
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+	(DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
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 struct ddc_registers {
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 	struct gpio_registers gpio;
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 	uint32_t ddc_setup;
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+	uint32_t phy_aux_cntl;
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+	uint32_t dc_gpio_aux_ctrl_5;
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 };
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 struct ddc_sh_mask {
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@@ -113,6 +132,9 @@
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 	/* i2cpad_mask */
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 	uint32_t DC_GPIO_SDA_PD_DIS;
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 	uint32_t DC_GPIO_SCL_PD_DIS;
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+	//phy_aux_cntl
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+	uint32_t AUX_PAD_RXSEL;
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+	uint32_t DDC_PAD_I2CMODE;
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 };
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@@ -148,6 +170,25 @@
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 {\
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 	DDC_I2C_REG_LIST(SCL)\
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 }
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+#define ddc_data_regs_dcn2(id) \
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+{\
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+	DDC_REG_LIST_DCN2(DATA, id)\
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+}
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+
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+#define ddc_clk_regs_dcn2(id) \
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+{\
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+	DDC_REG_LIST_DCN2(CLK, id)\
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+}
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+
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+#define ddc_i2c_data_regs_dcn2 \
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+{\
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+	DDC_I2C_REG_LIST_DCN2(SDA)\
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+}
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+
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+#define ddc_i2c_clk_regs_dcn2 \
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+{\
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+	DDC_REG_LIST_DCN2(SCL)\
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+}
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 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */