disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
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@@ -37,11 +37,14 @@
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 	dm_444_64 = 2,
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 	dm_420_8 = 3,
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 	dm_420_10 = 4,
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-	dm_422_8 = 5,
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-	dm_422_10 = 6,
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-	dm_444_8 = 7,
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-	dm_mono_8,
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-	dm_mono_16
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+	dm_420_12 = 5,
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+	dm_422_8 = 6,
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+	dm_422_10 = 7,
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+	dm_444_8 = 8,
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+	dm_mono_8 = dm_444_8,
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+	dm_mono_16 = dm_444_16,
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+	dm_rgbe = 9,
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+	dm_rgbe_alpha = 10,
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 };
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 enum output_bpc_class {
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 	dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
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@@ -77,16 +80,17 @@
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 	dm_sw_SPARE_13 = 24,
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 	dm_sw_64kb_s_x = 25,
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 	dm_sw_64kb_d_x = 26,
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-	dm_sw_SPARE_14 = 27,
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+	dm_sw_64kb_r_x = 27,
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 	dm_sw_SPARE_15 = 28,
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 	dm_sw_var_s_x = 29,
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 	dm_sw_var_d_x = 30,
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-	dm_sw_64kb_r_x,
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-	dm_sw_gfx7_2d_thin_lvp,
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-	dm_sw_gfx7_2d_thin_gl
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+	dm_sw_var_r_x = 31,
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+	dm_sw_gfx7_2d_thin_l_vp,
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+	dm_sw_gfx7_2d_thin_gl,
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 };
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 enum lb_depth {
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-	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16
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+	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
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+	dm_lb_19 = 5
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 };
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 enum voltage_state {
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 	dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
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@@ -111,7 +115,12 @@
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 enum mpc_combine_affinity {
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 	dm_mpc_always_when_possible,
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 	dm_mpc_reduce_voltage,
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-	dm_mpc_reduce_voltage_and_clocks
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+	dm_mpc_reduce_voltage_and_clocks,
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+	dm_mpc_never
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+};
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+
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+enum RequestType {
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+	REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
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 };
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 enum self_refresh_affinity {
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@@ -121,4 +130,61 @@
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 	dm_neither_self_refresh_nor_mclk_switch
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 };
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+enum dm_validation_status {
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+	DML_VALIDATION_OK,
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+	DML_FAIL_SCALE_RATIO_TAP,
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+	DML_FAIL_SOURCE_PIXEL_FORMAT,
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+	DML_FAIL_VIEWPORT_SIZE,
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+	DML_FAIL_TOTAL_V_ACTIVE_BW,
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+	DML_FAIL_DIO_SUPPORT,
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+	DML_FAIL_NOT_ENOUGH_DSC,
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+	DML_FAIL_DSC_CLK_REQUIRED,
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+	DML_FAIL_DSC_VALIDATION_FAILURE,
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+	DML_FAIL_URGENT_LATENCY,
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+	DML_FAIL_REORDERING_BUFFER,
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+	DML_FAIL_DISPCLK_DPPCLK,
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+	DML_FAIL_TOTAL_AVAILABLE_PIPES,
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+	DML_FAIL_NUM_OTG,
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+	DML_FAIL_WRITEBACK_MODE,
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+	DML_FAIL_WRITEBACK_LATENCY,
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+	DML_FAIL_WRITEBACK_SCALE_RATIO_TAP,
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+	DML_FAIL_CURSOR_SUPPORT,
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+	DML_FAIL_PITCH_SUPPORT,
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+	DML_FAIL_PTE_BUFFER_SIZE,
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+	DML_FAIL_HOST_VM_IMMEDIATE_FLIP,
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+	DML_FAIL_DSC_INPUT_BPC,
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+	DML_FAIL_PREFETCH_SUPPORT,
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+	DML_FAIL_V_RATIO_PREFETCH,
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+};
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+
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+enum writeback_config {
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+	dm_normal,
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+	dm_whole_buffer_for_single_stream_no_interleave,
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+	dm_whole_buffer_for_single_stream_interleave,
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+};
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+
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+enum odm_combine_mode {
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+	dm_odm_combine_mode_disabled,
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+	dm_odm_combine_mode_2to1,
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+	dm_odm_combine_mode_4to1,
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+};
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+
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+enum odm_combine_policy {
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+	dm_odm_combine_policy_dal,
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+	dm_odm_combine_policy_none,
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+	dm_odm_combine_policy_2to1,
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+	dm_odm_combine_policy_4to1,
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+};
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+
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+enum immediate_flip_requirement {
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+	dm_immediate_flip_not_required,
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+	dm_immediate_flip_required,
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+};
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+
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+enum unbounded_requesting_policy {
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+	dm_unbounded_requesting,
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+	dm_unbounded_requesting_edp_only,
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+	dm_unbounded_requesting_disable
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+};
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+
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 #endif