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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
....@@ -30,103 +30,263 @@
3030  * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
3131  */
3232 
33
+enum pp_smu_ver {
34
+	/*
35
+	 * PP_SMU_INTERFACE_X should be interpreted as the interface defined
36
+	 * starting from X, where X is some family of ASICs.  This is as
37
+	 * opposed to interfaces used only for X.  There will be some degree
38
+	 * of interface sharing between families of ASIcs.
39
+	 */
40
+	PP_SMU_UNSUPPORTED,
41
+	PP_SMU_VER_RV,
42
+	PP_SMU_VER_NV,
43
+	PP_SMU_VER_RN,
44
+
45
+	PP_SMU_VER_MAX
46
+};
3347 
3448 struct pp_smu {
35
-	struct dc_context *ctx;
49
+	enum pp_smu_ver ver;
50
+	const void *pp;
51
+
52
+	/*
53
+	 * interim extra handle for backwards compatibility
54
+	 * as some existing functionality not yet implemented
55
+	 * by ppsmu
56
+	 */
57
+	const void *dm;
3658 };
3759 
38
-enum wm_set_id {
39
-	WM_A,
40
-	WM_B,
41
-	WM_C,
42
-	WM_D,
43
-	WM_SET_COUNT,
60
+enum pp_smu_status {
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+	PP_SMU_RESULT_UNDEFINED = 0,
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+	PP_SMU_RESULT_OK = 1,
63
+	PP_SMU_RESULT_FAIL,
64
+	PP_SMU_RESULT_UNSUPPORTED
4465 };
4566 
67
+#define PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN 0x0
68
+#define PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX 0xFFFF
69
+
70
+enum wm_type {
71
+	WM_TYPE_PSTATE_CHG = 0,
72
+	WM_TYPE_RETRAINING = 1,
73
+};
74
+
75
+/* This structure is a copy of WatermarkRowGeneric_t defined by smuxx_driver_if.h*/
4676 struct pp_smu_wm_set_range {
47
-	enum wm_set_id wm_inst;
48
-	uint32_t min_fill_clk_khz;
49
-	uint32_t max_fill_clk_khz;
50
-	uint32_t min_drain_clk_khz;
51
-	uint32_t max_drain_clk_khz;
77
+	uint16_t min_fill_clk_mhz;
78
+	uint16_t max_fill_clk_mhz;
79
+	uint16_t min_drain_clk_mhz;
80
+	uint16_t max_drain_clk_mhz;
81
+
82
+	uint8_t wm_inst;
83
+	uint8_t wm_type;
5284 };
85
+
86
+#define MAX_WATERMARK_SETS 4
5387 
5488 struct pp_smu_wm_range_sets {
55
-	uint32_t num_reader_wm_sets;
56
-	struct pp_smu_wm_set_range reader_wm_sets[WM_SET_COUNT];
89
+	unsigned int num_reader_wm_sets;
90
+	struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS];
5791 
58
-	uint32_t num_writer_wm_sets;
59
-	struct pp_smu_wm_set_range writer_wm_sets[WM_SET_COUNT];
60
-};
61
-
62
-struct pp_smu_display_requirement_rv {
63
-	/* PPSMC_MSG_SetDisplayCount: count
64
-	 *  0 triggers S0i2 optimization
65
-	 */
66
-	unsigned int display_count;
67
-
68
-	/* PPSMC_MSG_SetHardMinFclkByFreq: khz
69
-	 *  FCLK will vary with DPM, but never below requested hard min
70
-	 */
71
-	unsigned int hard_min_fclk_khz;
72
-
73
-	/* PPSMC_MSG_SetHardMinDcefclkByFreq: khz
74
-	 *  fixed clock at requested freq, either from FCH bypass or DFS
75
-	 */
76
-	unsigned int hard_min_dcefclk_khz;
77
-
78
-	/* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz
79
-	 *  when DF is in cstate, dcf clock is further divided down
80
-	 *  to just above given frequency
81
-	 */
82
-	unsigned int min_deep_sleep_dcefclk_mhz;
92
+	unsigned int num_writer_wm_sets;
93
+	struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS];
8394 };
8495 
8596 struct pp_smu_funcs_rv {
8697 	struct pp_smu pp_smu;
8798 
88
-	void (*set_display_requirement)(struct pp_smu *pp,
89
-			struct pp_smu_display_requirement_rv *req);
99
+	/* PPSMC_MSG_SetDisplayCount
100
+	 * 0 triggers S0i2 optimization
101
+	 */
90102 
91
-	/* which SMU message?  are reader and writer WM separate SMU msg? */
103
+	void (*set_display_count)(struct pp_smu *pp, int count);
104
+
105
+	/* reader and writer WM's are sent together as part of one table*/
106
+	/*
107
+	 * PPSMC_MSG_SetDriverDramAddrHigh
108
+	 * PPSMC_MSG_SetDriverDramAddrLow
109
+	 * PPSMC_MSG_TransferTableDram2Smu
110
+	 *
111
+	 * */
92112 	void (*set_wm_ranges)(struct pp_smu *pp,
93113 			struct pp_smu_wm_range_sets *ranges);
114
+
115
+	/* PPSMC_MSG_SetHardMinDcfclkByFreq
116
+	 * fixed clock at requested freq, either from FCH bypass or DFS
117
+	 */
118
+	void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
119
+
120
+	/* PPSMC_MSG_SetMinDeepSleepDcfclk
121
+	 * when DF is in cstate, dcf clock is further divided down
122
+	 * to just above given frequency
123
+	 */
124
+	void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
125
+
126
+	/* PPSMC_MSG_SetHardMinFclkByFreq
127
+	 * FCLK will vary with DPM, but never below requested hard min
128
+	 */
129
+	void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
130
+
131
+	/* PPSMC_MSG_SetHardMinSocclkByFreq
132
+	 * Needed for DWB support
133
+	 */
134
+	void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
135
+
94136 	/* PME w/a */
95137 	void (*set_pme_wa_enable)(struct pp_smu *pp);
96138 };
97139 
98
-#if 0
99
-struct pp_smu_funcs_rv {
140
+/* Used by pp_smu_funcs_nv.set_voltage_by_freq
141
+ *
142
+ */
143
+enum pp_smu_nv_clock_id {
144
+	PP_SMU_NV_DISPCLK,
145
+	PP_SMU_NV_PHYCLK,
146
+	PP_SMU_NV_PIXELCLK
147
+};
148
+
149
+/*
150
+ * Used by pp_smu_funcs_nv.get_maximum_sustainable_clocks
151
+ */
152
+struct pp_smu_nv_clock_table {
153
+	// voltage managed SMU, freq set by driver
154
+	unsigned int    displayClockInKhz;
155
+	unsigned int	dppClockInKhz;
156
+	unsigned int    phyClockInKhz;
157
+	unsigned int    pixelClockInKhz;
158
+	unsigned int	dscClockInKhz;
159
+
160
+	// freq/voltage managed by SMU
161
+	unsigned int	fabricClockInKhz;
162
+	unsigned int	socClockInKhz;
163
+	unsigned int    dcfClockInKhz;
164
+	unsigned int    uClockInKhz;
165
+};
166
+
167
+struct pp_smu_funcs_nv {
168
+	struct pp_smu pp_smu;
100169 
101170 	/* PPSMC_MSG_SetDisplayCount
102
-	 *  0 triggers S0i2 optimization
171
+	 * 0 triggers S0i2 optimization
103172 	 */
104
-	void (*set_display_count)(struct pp_smu *pp, int count);
173
+	enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);
105174 
106
-	/* PPSMC_MSG_SetHardMinFclkByFreq
107
-	 *  FCLK will vary with DPM, but never below requested hard min
175
+	/* PPSMC_MSG_SetHardMinDcfclkByFreq
176
+	 * fixed clock at requested freq, either from FCH bypass or DFS
108177 	 */
109
-	void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz);
178
+	enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);
110179 
111
-	/* PPSMC_MSG_SetHardMinDcefclkByFreq
112
-	 *  fixed clock at requested freq, either from FCH bypass or DFS
180
+	/* PPSMC_MSG_SetMinDeepSleepDcfclk
181
+	 * when DF is in cstate, dcf clock is further divided down
182
+	 * to just above given frequency
113183 	 */
114
-	void (*set_hard_min_dcefclk_by_freq)(struct pp_smu *pp, int khz);
184
+	enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);
115185 
116
-	/* PPSMC_MSG_SetMinDeepSleepDcefclk
117
-	 *  when DF is in cstate, dcf clock is further divided down
118
-	 *  to just above given frequency
186
+	/* PPSMC_MSG_SetHardMinUclkByFreq
187
+	 * UCLK will vary with DPM, but never below requested hard min
119188 	 */
120
-	void (*set_min_deep_sleep_dcefclk)(struct pp_smu *pp, int mhz);
189
+	enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);
121190 
122
-	/* todo: aesthetic
123
-	 * watermark range table
191
+	/* PPSMC_MSG_SetHardMinSocclkByFreq
192
+	 * Needed for DWB support
124193 	 */
194
+	enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);
125195 
126
-	/* todo: functional/feature
127
-	 * PPSMC_MSG_SetHardMinSocclkByFreq: required to support DWB
196
+	/* PME w/a */
197
+	enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);
198
+
199
+	/* PPSMC_MSG_SetHardMinByFreq
200
+	 * Needed to set ASIC voltages for clocks programmed by DAL
128201 	 */
202
+	enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,
203
+			enum pp_smu_nv_clock_id clock_id, int Mhz);
204
+
205
+	/* reader and writer WM's are sent together as part of one table*/
206
+	/*
207
+	 * PPSMC_MSG_SetDriverDramAddrHigh
208
+	 * PPSMC_MSG_SetDriverDramAddrLow
209
+	 * PPSMC_MSG_TransferTableDram2Smu
210
+	 *
211
+	 * on DCN20:
212
+	 * 	reader fill clk = uclk
213
+	 * 	reader drain clk = dcfclk
214
+	 * 	writer fill clk = socclk
215
+	 * 	writer drain clk = uclk
216
+	 * */
217
+	enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
218
+			struct pp_smu_wm_range_sets *ranges);
219
+
220
+	/* Not a single SMU message.  This call should return maximum sustainable limit for all
221
+	 * clocks that DC depends on.  These will be used as basis for mode enumeration.
222
+	 */
223
+	enum pp_smu_status (*get_maximum_sustainable_clocks)(struct pp_smu *pp,
224
+			struct pp_smu_nv_clock_table *max_clocks);
225
+
226
+	/* This call should return the discrete uclk DPM states available
227
+	 */
228
+	enum pp_smu_status (*get_uclk_dpm_states)(struct pp_smu *pp,
229
+			unsigned int *clock_values_in_khz, unsigned int *num_states);
230
+
231
+	/* Not a single SMU message.  This call informs PPLIB that display will not be able
232
+	 * to perform pstate handshaking in its current state.  Typically this handshake
233
+	 * is used to perform uCLK switching, so disabling pstate disables uCLK switching.
234
+	 *
235
+	 * Note that when setting handshake to unsupported, the call is pre-emptive.  That means
236
+	 * DC will make the call BEFORE setting up the display state which would cause pstate
237
+	 * request to go un-acked.  Only when the call completes should such a state be applied to
238
+	 * DC hardware
239
+	 */
240
+	enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,
241
+			bool pstate_handshake_supported);
129242 };
130
-#endif
243
+
244
+#define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
245
+#define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
246
+#define PP_SMU_NUM_FCLK_DPM_LEVELS    4
247
+#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
248
+
249
+struct dpm_clock {
250
+  uint32_t  Freq;    // In MHz
251
+  uint32_t  Vol;     // Millivolts with 2 fractional bits
252
+};
253
+
254
+
255
+/* this is a copy of the structure defined in smuxx_driver_if.h*/
256
+struct dpm_clocks {
257
+	struct dpm_clock DcfClocks[PP_SMU_NUM_DCFCLK_DPM_LEVELS];
258
+	struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS];
259
+	struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS];
260
+	struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS];
261
+};
262
+
263
+
264
+struct pp_smu_funcs_rn {
265
+	struct pp_smu pp_smu;
266
+
267
+	/*
268
+	 * reader and writer WM's are sent together as part of one table
269
+	 *
270
+	 * PPSMC_MSG_SetDriverDramAddrHigh
271
+	 * PPSMC_MSG_SetDriverDramAddrLow
272
+	 * PPSMC_MSG_TransferTableDram2Smu
273
+	 *
274
+	 */
275
+	enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
276
+			struct pp_smu_wm_range_sets *ranges);
277
+
278
+	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
279
+			struct dpm_clocks *clock_table);
280
+};
281
+
282
+struct pp_smu_funcs {
283
+	struct pp_smu ctx;
284
+	union {
285
+		struct pp_smu_funcs_rv rv_funcs;
286
+		struct pp_smu_funcs_nv nv_funcs;
287
+		struct pp_smu_funcs_rn rn_funcs;
288
+
289
+	};
290
+};
131291 
132292 #endif /* DM_PP_SMU_IF__H */