disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
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@@ -31,10 +31,10 @@
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 #define TO_DCN10_LINK_ENC(link_encoder)\
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 	container_of(link_encoder, struct dcn10_link_encoder, base)
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-
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 #define AUX_REG_LIST(id)\
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 	SRI(AUX_CONTROL, DP_AUX, id), \
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-	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
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+	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
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+	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
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38
 
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 #define HPD_REG_LIST(id)\
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 	SRI(DC_HPD_CONTROL, HPD, id)
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@@ -62,16 +62,18 @@
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 	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
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 	SRI(DP_SEC_CNTL1, DP, id), \
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 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
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-	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
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 #define LE_DCN10_REG_LIST(id)\
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+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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 	LE_DCN_COMMON_REG_LIST(id)
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 struct dcn10_link_enc_aux_registers {
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 	uint32_t AUX_CONTROL;
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 	uint32_t AUX_DPHY_RX_CONTROL0;
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+	uint32_t AUX_DPHY_TX_CONTROL;
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+	uint32_t AUX_DPHY_RX_CONTROL1;
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 };
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 struct dcn10_link_enc_hpd_registers {
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@@ -103,6 +105,61 @@
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 	uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
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 	uint32_t DP_SEC_CNTL1;
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 	uint32_t TMDS_CTL_BITS;
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+	/* DCCG  */
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+	uint32_t CLOCK_ENABLE;
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+	/* DIG */
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+	uint32_t DIG_LANE_ENABLE;
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+	/* UNIPHY */
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+	uint32_t CHANNEL_XBAR_CNTL;
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+	/* DPCS */
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+	uint32_t RDPCSTX_PHY_CNTL3;
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+	uint32_t RDPCSTX_PHY_CNTL4;
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+	uint32_t RDPCSTX_PHY_CNTL5;
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+	uint32_t RDPCSTX_PHY_CNTL6;
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+	uint32_t RDPCSTX_PHY_CNTL7;
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+	uint32_t RDPCSTX_PHY_CNTL8;
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+	uint32_t RDPCSTX_PHY_CNTL9;
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+	uint32_t RDPCSTX_PHY_CNTL10;
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+	uint32_t RDPCSTX_PHY_CNTL11;
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+	uint32_t RDPCSTX_PHY_CNTL12;
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+	uint32_t RDPCSTX_PHY_CNTL13;
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+	uint32_t RDPCSTX_PHY_CNTL14;
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+	uint32_t RDPCSTX_PHY_CNTL15;
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+	uint32_t RDPCSTX_CNTL;
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+	uint32_t RDPCSTX_CLOCK_CNTL;
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+	uint32_t RDPCSTX_PHY_CNTL0;
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+	uint32_t RDPCSTX_PHY_CNTL2;
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+	uint32_t RDPCSTX_PLL_UPDATE_DATA;
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+	uint32_t RDPCS_TX_CR_ADDR;
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+	uint32_t RDPCS_TX_CR_DATA;
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+	uint32_t DPCSTX_TX_CLOCK_CNTL;
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+	uint32_t DPCSTX_TX_CNTL;
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+	uint32_t RDPCSTX_INTERRUPT_CONTROL;
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+	uint32_t RDPCSTX_PHY_FUSE0;
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+	uint32_t RDPCSTX_PHY_FUSE1;
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+	uint32_t RDPCSTX_PHY_FUSE2;
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+	uint32_t RDPCSTX_PHY_FUSE3;
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+	uint32_t RDPCSTX_PHY_RX_LD_VAL;
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+	uint32_t DPCSTX_DEBUG_CONFIG;
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+	uint32_t RDPCSTX_DEBUG_CONFIG;
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+	uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
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+	uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
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+	uint32_t DCIO_SOFT_RESET;
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+	/* indirect registers */
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+	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
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+	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
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+	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
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+	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
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+	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
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+	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
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+	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
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+	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
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+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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+	uint32_t TMDS_DCBALANCER_CONTROL;
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+	uint32_t PHYA_LINK_CNTL2;
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+	uint32_t PHYB_LINK_CNTL2;
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+	uint32_t PHYC_LINK_CNTL2;
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+#endif
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 };
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 #define LE_SF(reg_name, field_name, post_fix)\
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@@ -208,12 +265,198 @@
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 	type AUX_LS_READ_EN;\
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 	type AUX_RX_RECEIVE_WINDOW
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+
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+#define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
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+		type RDPCS_PHY_DP_TX0_DATA_EN;\
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+		type RDPCS_PHY_DP_TX1_DATA_EN;\
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+		type RDPCS_PHY_DP_TX2_DATA_EN;\
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+		type RDPCS_PHY_DP_TX3_DATA_EN;\
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+		type RDPCS_PHY_DP_TX0_PSTATE;\
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+		type RDPCS_PHY_DP_TX1_PSTATE;\
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+		type RDPCS_PHY_DP_TX2_PSTATE;\
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+		type RDPCS_PHY_DP_TX3_PSTATE;\
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+		type RDPCS_PHY_DP_TX0_MPLL_EN;\
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+		type RDPCS_PHY_DP_TX1_MPLL_EN;\
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+		type RDPCS_PHY_DP_TX2_MPLL_EN;\
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+		type RDPCS_PHY_DP_TX3_MPLL_EN;\
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+		type RDPCS_TX_FIFO_LANE0_EN;\
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+		type RDPCS_TX_FIFO_LANE1_EN;\
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+		type RDPCS_TX_FIFO_LANE2_EN;\
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+		type RDPCS_TX_FIFO_LANE3_EN;\
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+		type RDPCS_EXT_REFCLK_EN;\
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+		type RDPCS_TX_FIFO_EN;\
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+		type UNIPHY_LINK_ENABLE;\
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+		type UNIPHY_CHANNEL0_XBAR_SOURCE;\
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+		type UNIPHY_CHANNEL1_XBAR_SOURCE;\
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+		type UNIPHY_CHANNEL2_XBAR_SOURCE;\
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+		type UNIPHY_CHANNEL3_XBAR_SOURCE;\
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+		type UNIPHY_CHANNEL0_INVERT;\
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+		type UNIPHY_CHANNEL1_INVERT;\
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+		type UNIPHY_CHANNEL2_INVERT;\
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+		type UNIPHY_CHANNEL3_INVERT;\
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+		type UNIPHY_LINK_ENABLE_HPD_MASK;\
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+		type UNIPHY_LANE_STAGGER_DELAY;\
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+		type RDPCS_SRAMCLK_BYPASS;\
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+		type RDPCS_SRAMCLK_EN;\
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+		type RDPCS_SRAMCLK_CLOCK_ON;\
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+		type DPCS_TX_FIFO_EN;\
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+		type RDPCS_PHY_DP_TX0_DISABLE;\
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+		type RDPCS_PHY_DP_TX1_DISABLE;\
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+		type RDPCS_PHY_DP_TX2_DISABLE;\
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+		type RDPCS_PHY_DP_TX3_DISABLE;\
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+		type RDPCS_PHY_DP_TX0_CLK_RDY;\
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+		type RDPCS_PHY_DP_TX1_CLK_RDY;\
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+		type RDPCS_PHY_DP_TX2_CLK_RDY;\
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+		type RDPCS_PHY_DP_TX3_CLK_RDY;\
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+		type RDPCS_PHY_DP_TX0_REQ;\
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+		type RDPCS_PHY_DP_TX1_REQ;\
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+		type RDPCS_PHY_DP_TX2_REQ;\
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+		type RDPCS_PHY_DP_TX3_REQ;\
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+		type RDPCS_PHY_DP_TX0_ACK;\
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+		type RDPCS_PHY_DP_TX1_ACK;\
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+		type RDPCS_PHY_DP_TX2_ACK;\
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+		type RDPCS_PHY_DP_TX3_ACK;\
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+		type RDPCS_PHY_DP_TX0_RESET;\
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+		type RDPCS_PHY_DP_TX1_RESET;\
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+		type RDPCS_PHY_DP_TX2_RESET;\
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+		type RDPCS_PHY_DP_TX3_RESET;\
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+		type RDPCS_PHY_RESET;\
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+		type RDPCS_PHY_CR_MUX_SEL;\
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+		type RDPCS_PHY_REF_RANGE;\
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+		type RDPCS_PHY_DP4_POR;\
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+		type RDPCS_SRAM_BYPASS;\
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+		type RDPCS_SRAM_EXT_LD_DONE;\
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+		type RDPCS_PHY_DP_TX0_TERM_CTRL;\
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+		type RDPCS_PHY_DP_TX1_TERM_CTRL;\
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+		type RDPCS_PHY_DP_TX2_TERM_CTRL;\
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+		type RDPCS_PHY_DP_TX3_TERM_CTRL;\
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+		type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
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+		type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
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+		type RDPCS_PHY_DP_MPLLB_SSC_EN;\
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+		type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
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+		type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
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+		type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
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+		type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
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+		type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
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+		type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
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+		type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
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+		type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
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+		type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
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+		type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
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+		type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
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+		type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
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+		type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
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+		type RDPCS_PHY_TX_VBOOST_LVL;\
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+		type RDPCS_PHY_HDMIMODE_ENABLE;\
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+		type RDPCS_PHY_DP_REF_CLK_EN;\
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+		type RDPCS_PLL_UPDATE_DATA;\
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+		type RDPCS_SRAM_INIT_DONE;\
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+		type RDPCS_TX_CR_ADDR;\
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+		type RDPCS_TX_CR_DATA;\
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+		type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
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+		type RDPCS_PHY_DP_MPLLB_STATE;\
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+		type RDPCS_PHY_DP_TX0_WIDTH;\
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+		type RDPCS_PHY_DP_TX0_RATE;\
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+		type RDPCS_PHY_DP_TX1_WIDTH;\
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+		type RDPCS_PHY_DP_TX1_RATE;\
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+		type RDPCS_PHY_DP_TX2_WIDTH;\
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+		type RDPCS_PHY_DP_TX2_RATE;\
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+		type RDPCS_PHY_DP_TX3_WIDTH;\
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+		type RDPCS_PHY_DP_TX3_RATE;\
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+		type DPCS_SYMCLK_CLOCK_ON;\
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+		type DPCS_SYMCLK_GATE_DIS;\
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+		type DPCS_SYMCLK_EN;\
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+		type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
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+		type RDPCS_SYMCLK_DIV2_GATE_DIS;\
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+		type RDPCS_SYMCLK_DIV2_EN;\
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+		type DPCS_TX_DATA_SWAP;\
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+		type DPCS_TX_DATA_ORDER_INVERT;\
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+		type DPCS_TX_FIFO_RD_START_DELAY;\
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+		type RDPCS_TX_FIFO_RD_START_DELAY;\
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+		type RDPCS_REG_FIFO_ERROR_MASK;\
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+		type RDPCS_TX_FIFO_ERROR_MASK;\
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+		type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
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+		type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
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+		type RDPCS_PHY_DPALT_DP4;\
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+		type RDPCS_PHY_DPALT_DISABLE;\
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+		type RDPCS_PHY_DPALT_DISABLE_ACK;\
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+		type RDPCS_PHY_DP_MPLLB_V2I;\
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+		type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
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+		type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
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+		type RDPCS_PHY_RX_VREF_CTRL;\
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+		type RDPCS_PHY_DP_MPLLB_CP_INT;\
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+		type RDPCS_PHY_DP_MPLLB_CP_PROP;\
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+		type RDPCS_PHY_RX_REF_LD_VAL;\
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+		type RDPCS_PHY_RX_VCO_LD_VAL;\
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+		type DPCSTX_DEBUG_CONFIG; \
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+		type RDPCSTX_DEBUG_CONFIG; \
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+		type RDPCS_PHY_DP_TX0_EQ_MAIN;\
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+		type RDPCS_PHY_DP_TX0_EQ_PRE;\
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+		type RDPCS_PHY_DP_TX0_EQ_POST;\
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+		type RDPCS_PHY_DP_TX1_EQ_MAIN;\
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+		type RDPCS_PHY_DP_TX1_EQ_PRE;\
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+		type RDPCS_PHY_DP_TX1_EQ_POST;\
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+		type RDPCS_PHY_DP_TX2_EQ_MAIN;\
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+		type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
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+		type RDPCS_PHY_DP_TX2_EQ_PRE;\
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+		type RDPCS_PHY_DP_TX2_EQ_POST;\
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+		type RDPCS_PHY_DP_TX3_EQ_MAIN;\
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+		type RDPCS_PHY_DCO_RANGE;\
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+		type RDPCS_PHY_DCO_FINETUNE;\
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+		type RDPCS_PHY_DP_TX3_EQ_PRE;\
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+		type RDPCS_PHY_DP_TX3_EQ_POST;\
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+		type RDPCS_PHY_SUP_PRE_HP;\
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+		type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
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+		type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
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+		type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
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+		type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
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+		type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
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+		type UNIPHYA_SOFT_RESET;\
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+		type UNIPHYB_SOFT_RESET;\
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+		type UNIPHYC_SOFT_RESET;\
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+		type UNIPHYD_SOFT_RESET;\
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+		type UNIPHYE_SOFT_RESET;\
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+		type UNIPHYF_SOFT_RESET
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+
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+#define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
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+	type DIG_LANE0EN;\
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+	type DIG_LANE1EN;\
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+	type DIG_LANE2EN;\
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+	type DIG_LANE3EN;\
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+	type DIG_CLK_EN;\
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+	type SYMCLKA_CLOCK_ENABLE;\
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+	type DPHY_FEC_EN;\
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+	type DPHY_FEC_READY_SHADOW;\
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+	type DPHY_FEC_ACTIVE_STATUS;\
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+	DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
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+	type VCO_LD_VAL_OVRD;\
433
+	type VCO_LD_VAL_OVRD_EN;\
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+	type REF_LD_VAL_OVRD;\
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+	type REF_LD_VAL_OVRD_EN;\
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+	type AUX_RX_START_WINDOW; \
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+	type AUX_RX_HALF_SYM_DETECT_LEN; \
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+	type AUX_RX_TRANSITION_FILTER_EN; \
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+	type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
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+	type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
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+	type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
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+	type AUX_RX_PHASE_DETECT_LEN; \
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+	type AUX_RX_DETECTION_THRESHOLD; \
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+	type AUX_TX_PRECHARGE_LEN; \
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+	type AUX_TX_PRECHARGE_SYMBOLS; \
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+	type AUX_MODE_DET_CHECK_DELAY;\
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+	type DPCS_DBG_CBUS_DIS;\
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+	type AUX_RX_PRECHARGE_SKIP;\
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+	type AUX_RX_TIMEOUT_LEN;\
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+	type AUX_RX_TIMEOUT_LEN_MUL
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+
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 struct dcn10_link_enc_shift {
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 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
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+	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
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 };
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456
 
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 struct dcn10_link_enc_mask {
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 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
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+	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
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 };
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461
 
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 struct dcn10_link_encoder {
..
..
@@ -271,7 +514,7 @@
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 	struct link_encoder *enc,
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 	enum signal_type signal);
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516
 
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-void configure_encoder(
517
+void enc1_configure_encoder(
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 	struct dcn10_link_encoder *enc10,
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519
 	const struct dc_link_settings *link_settings);
277
520
 
..
..
@@ -336,6 +579,13 @@
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579
 
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580
 bool dcn10_is_dig_enabled(struct link_encoder *enc);
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581
 
582
+unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
583
+
339
584
 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
340
585
 
586
+enum signal_type dcn10_get_dig_mode(
587
+	struct link_encoder *enc);
588
+
589
+void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
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+	struct dc_link_settings *link_settings);
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591
 #endif /* __DC_LINK_ENCODER__DCN10_H__ */