forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
....@@ -29,18 +29,17 @@
2929 #include "core_types.h"
3030 #include "dchubbub.h"
3131 
32
-#define HUBHUB_REG_LIST_DCN()\
32
+#define TO_DCN10_HUBBUB(hubbub)\
33
+	container_of(hubbub, struct dcn10_hubbub, base)
34
+
35
+#define HUBBUB_REG_LIST_DCN_COMMON()\
3336 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
34
-	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
3537 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
3638 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
37
-	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
3839 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
3940 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
40
-	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
4141 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
4242 	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
43
-	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
4443 	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
4544 	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
4645 	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
....@@ -50,6 +49,12 @@
5049 	SR(DCHUBBUB_TEST_DEBUG_INDEX), \
5150 	SR(DCHUBBUB_TEST_DEBUG_DATA),\
5251 	SR(DCHUBBUB_SOFT_RESET)
52
+
53
+#define HUBBUB_VM_REG_LIST() \
54
+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
55
+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
56
+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
57
+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)
5358 
5459 #define HUBBUB_SR_WATERMARK_REG_LIST()\
5560 	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
....@@ -62,7 +67,8 @@
6267 	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
6368 
6469 #define HUBBUB_REG_LIST_DCN10(id)\
65
-	HUBHUB_REG_LIST_DCN(), \
70
+	HUBBUB_REG_LIST_DCN_COMMON(), \
71
+	HUBBUB_VM_REG_LIST(), \
6672 	HUBBUB_SR_WATERMARK_REG_LIST(), \
6773 	SR(DCHUBBUB_SDPIF_FB_TOP),\
6874 	SR(DCHUBBUB_SDPIF_FB_BASE),\
....@@ -107,14 +113,39 @@
107113 	uint32_t DCHUBBUB_SDPIF_AGP_TOP;
108114 	uint32_t DCHUBBUB_CRC_CTRL;
109115 	uint32_t DCHUBBUB_SOFT_RESET;
116
+	uint32_t DCN_VM_FB_LOCATION_BASE;
117
+	uint32_t DCN_VM_FB_LOCATION_TOP;
118
+	uint32_t DCN_VM_FB_OFFSET;
119
+	uint32_t DCN_VM_AGP_BOT;
120
+	uint32_t DCN_VM_AGP_TOP;
121
+	uint32_t DCN_VM_AGP_BASE;
122
+	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
123
+	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
124
+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;
125
+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;
126
+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
127
+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;
128
+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;
129
+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;
130
+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;
131
+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;
132
+	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;
133
+	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;
134
+	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;
135
+	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;
136
+	uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
137
+	uint32_t DCHVM_CTRL0;
138
+	uint32_t DCHVM_MEM_CTRL;
139
+	uint32_t DCHVM_CLK_CTRL;
140
+	uint32_t DCHVM_RIOMMU_CTRL0;
141
+	uint32_t DCHVM_RIOMMU_STAT0;
110142 };
111143 
112144 /* set field name */
113145 #define HUBBUB_SF(reg_name, field_name, post_fix)\
114146 	.field_name = reg_name ## __ ## field_name ## post_fix
115147 
116
-
117
-#define HUBBUB_MASK_SH_LIST_DCN(mask_sh)\
148
+#define HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh)\
118149 		HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
119150 		HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \
120151 		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
....@@ -124,10 +155,29 @@
124155 		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
125156 		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
126157 		HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
127
-		HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh)
158
+		HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
159
+		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \
160
+		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \
161
+		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \
162
+		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \
163
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \
164
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \
165
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \
166
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh)
167
+
168
+#define HUBBUB_MASK_SH_LIST_STUTTER(mask_sh) \
169
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \
170
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \
171
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \
172
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \
173
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \
174
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \
175
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \
176
+		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh)
128177 
129178 #define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\
130
-		HUBBUB_MASK_SH_LIST_DCN(mask_sh), \
179
+		HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
180
+		HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
131181 		HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
132182 		HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
133183 		HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
....@@ -152,35 +202,96 @@
152202 		type SDPIF_FB_OFFSET;\
153203 		type SDPIF_AGP_BASE;\
154204 		type SDPIF_AGP_BOT;\
155
-		type SDPIF_AGP_TOP
205
+		type SDPIF_AGP_TOP;\
206
+		type FB_BASE;\
207
+		type FB_TOP;\
208
+		type FB_OFFSET;\
209
+		type AGP_BOT;\
210
+		type AGP_TOP;\
211
+		type AGP_BASE;\
212
+		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\
213
+		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;\
214
+		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;\
215
+		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;\
216
+		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
217
+		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
218
+		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
219
+		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
220
+		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
221
+		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
156222 
223
+#define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
224
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
225
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;\
226
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;\
227
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;\
228
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;\
229
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;\
230
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\
231
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
232
+
233
+#define HUBBUB_HVM_REG_FIELD_LIST(type) \
234
+		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\
235
+		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\
236
+		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\
237
+		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\
238
+		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\
239
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\
240
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\
241
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\
242
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\
243
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\
244
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\
245
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\
246
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\
247
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
248
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
249
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
250
+		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
251
+		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\
252
+		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\
253
+		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\
254
+		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\
255
+		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\
256
+		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\
257
+		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\
258
+		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\
259
+		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\
260
+		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\
261
+		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\
262
+		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\
263
+		type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\
264
+		type HOSTVM_INIT_REQ; \
265
+		type HVM_GPUVMRET_PWR_REQ_DIS; \
266
+		type HVM_GPUVMRET_FORCE_REQ; \
267
+		type HVM_GPUVMRET_POWER_STATUS; \
268
+		type HVM_DISPCLK_R_GATE_DIS; \
269
+		type HVM_DISPCLK_G_GATE_DIS; \
270
+		type HVM_DCFCLK_R_GATE_DIS; \
271
+		type HVM_DCFCLK_G_GATE_DIS; \
272
+		type TR_REQ_REQCLKREQ_MODE; \
273
+		type TW_RSP_COMPCLKREQ_MODE; \
274
+		type HOSTVM_PREFETCH_REQ; \
275
+		type HOSTVM_POWERSTATUS; \
276
+		type RIOMMU_ACTIVE; \
277
+		type HOSTVM_PREFETCH_DONE
157278 
158279 struct dcn_hubbub_shift {
159280 	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
281
+	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
282
+	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
160283 };
161284 
162285 struct dcn_hubbub_mask {
163286 	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
287
+	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
288
+	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
164289 };
165290 
166291 struct dc;
167292 
168
-struct dcn_hubbub_wm_set {
169
-	uint32_t wm_set;
170
-	uint32_t data_urgent;
171
-	uint32_t pte_meta_urgent;
172
-	uint32_t sr_enter;
173
-	uint32_t sr_exit;
174
-	uint32_t dram_clk_chanage;
175
-};
176
-
177
-struct dcn_hubbub_wm {
178
-	struct dcn_hubbub_wm_set sets[4];
179
-};
180
-
181
-struct hubbub {
182
-	const struct hubbub_funcs *funcs;
183
-	struct dc_context *ctx;
293
+struct dcn10_hubbub {
294
+	struct hubbub base;
184295 	const struct dcn_hubbub_registers *regs;
185296 	const struct dcn_hubbub_shift *shifts;
186297 	const struct dcn_hubbub_mask *masks;
....@@ -197,11 +308,15 @@
197308 
198309 void hubbub1_wm_change_req_wa(struct hubbub *hubbub);
199310 
200
-void hubbub1_program_watermarks(
311
+bool hubbub1_program_watermarks(
201312 		struct hubbub *hubbub,
202313 		struct dcn_watermark_set *watermarks,
203314 		unsigned int refclk_mhz,
204315 		bool safe_to_lower);
316
+
317
+void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
318
+
319
+bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
205320 
206321 void hubbub1_toggle_watermark_change_req(
207322 		struct hubbub *hubbub);
....@@ -216,4 +331,20 @@
216331 	const struct dcn_hubbub_shift *hubbub_shift,
217332 	const struct dcn_hubbub_mask *hubbub_mask);
218333 
334
+bool hubbub1_program_urgent_watermarks(
335
+		struct hubbub *hubbub,
336
+		struct dcn_watermark_set *watermarks,
337
+		unsigned int refclk_mhz,
338
+		bool safe_to_lower);
339
+bool hubbub1_program_stutter_watermarks(
340
+		struct hubbub *hubbub,
341
+		struct dcn_watermark_set *watermarks,
342
+		unsigned int refclk_mhz,
343
+		bool safe_to_lower);
344
+bool hubbub1_program_pstate_watermarks(
345
+		struct hubbub *hubbub,
346
+		struct dcn_watermark_set *watermarks,
347
+		unsigned int refclk_mhz,
348
+		bool safe_to_lower);
349
+
219350 #endif