| .. | .. |
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| 469 | 469 | |
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| 470 | 470 | void dce110_timing_generator_set_static_screen_control( |
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| 471 | 471 | struct timing_generator *tg, |
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| 472 | | - uint32_t value) |
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| 472 | + uint32_t event_triggers, |
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| 473 | + uint32_t num_frames) |
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| 473 | 474 | { |
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| 474 | 475 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); |
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| 475 | 476 | uint32_t static_screen_cntl = 0; |
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| 476 | 477 | uint32_t addr = 0; |
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| 477 | 478 | |
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| 479 | + // By register spec, it only takes 8 bit value |
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| 480 | + if (num_frames > 0xFF) |
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| 481 | + num_frames = 0xFF; |
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| 482 | + |
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| 478 | 483 | addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL); |
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| 479 | 484 | static_screen_cntl = dm_read_reg(tg->ctx, addr); |
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| 480 | 485 | |
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| 481 | 486 | set_reg_field_value(static_screen_cntl, |
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| 482 | | - value, |
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| 487 | + event_triggers, |
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| 483 | 488 | CRTC_STATIC_SCREEN_CONTROL, |
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| 484 | 489 | CRTC_STATIC_SCREEN_EVENT_MASK); |
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| 485 | 490 | |
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| 486 | 491 | set_reg_field_value(static_screen_cntl, |
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| 487 | | - 2, |
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| 492 | + num_frames, |
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| 488 | 493 | CRTC_STATIC_SCREEN_CONTROL, |
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| 489 | 494 | CRTC_STATIC_SCREEN_FRAME_COUNT); |
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| 490 | 495 | |
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| .. | .. |
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| 1952 | 1957 | |
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| 1953 | 1958 | void dce110_tg_program_timing(struct timing_generator *tg, |
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| 1954 | 1959 | const struct dc_crtc_timing *timing, |
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| 1960 | + int vready_offset, |
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| 1961 | + int vstartup_start, |
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| 1962 | + int vupdate_offset, |
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| 1963 | + int vupdate_width, |
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| 1964 | + const enum signal_type signal, |
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| 1955 | 1965 | bool use_vbios) |
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| 1956 | 1966 | { |
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| 1957 | 1967 | if (use_vbios) |
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