disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
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@@ -58,6 +58,31 @@
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 	SRI(DVMM_PTE_CONTROL, DCP, id),\
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 	SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
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60
 
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define MI_DCE6_REG_LIST(id)\
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+	SRI(GRPH_ENABLE, DCP, id),\
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+	SRI(GRPH_CONTROL, DCP, id),\
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+	SRI(GRPH_X_START, DCP, id),\
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+	SRI(GRPH_Y_START, DCP, id),\
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+	SRI(GRPH_X_END, DCP, id),\
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+	SRI(GRPH_Y_END, DCP, id),\
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+	SRI(GRPH_PITCH, DCP, id),\
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+	SRI(GRPH_SWAP_CNTL, DCP, id),\
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+	SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
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+	SRI(GRPH_UPDATE, DCP, id),\
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+	SRI(GRPH_FLIP_CONTROL, DCP, id),\
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+	SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
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+	SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
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+	SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
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+	SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
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+	SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
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+	SRI(DPG_PIPE_ARBITRATION_CONTROL3, DMIF_PG, id),\
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+	SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id),\
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+	SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
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+	SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
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+	SRI(DMIF_BUFFER_CONTROL, PIPE, id)
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+#endif
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+
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 #define MI_DCE8_REG_LIST(id)\
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 	MI_DCE_BASE_REG_LIST(id),\
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 	SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
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@@ -104,6 +129,9 @@
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 	uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
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 	/* DMIF_PG */
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 	uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+	uint32_t DPG_PIPE_ARBITRATION_CONTROL3;
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+#endif
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 	uint32_t DPG_WATERMARK_MASK_CONTROL;
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 	uint32_t DPG_PIPE_URGENCY_CONTROL;
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 	uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
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@@ -125,6 +153,18 @@
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 /* Set_Filed_for_Block */
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 #define SFB(blk_name, reg_name, field_name, post_fix)\
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 	.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
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+
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define MI_GFX6_TILE_MASK_SH_LIST(mask_sh, blk)\
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+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
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+#endif
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 #define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
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 	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
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@@ -162,6 +202,32 @@
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 	SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
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 	SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
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204
 
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define MI_DCP_MASK_SH_LIST_DCE6(mask_sh, blk)\
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+	SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
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+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
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+	SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
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+	SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
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+	SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
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+	SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
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+	SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
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+	SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
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+	SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
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+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
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+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
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+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
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+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
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+	SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
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+	SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
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+	SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
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+	SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
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+	SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
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+	SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
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+	SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
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+#endif
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+
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 #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
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 	SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
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233
 
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@@ -171,6 +237,33 @@
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 	SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
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 	SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\
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 	SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh)
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+
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, blk)\
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+	SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
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+	SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
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+	SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
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+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
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+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
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+	SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
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+	SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
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+
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+#define MI_DMIF_PG_MASK_SH_DCE6(mask_sh, blk)\
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+	SFB(blk, DPG_PIPE_ARBITRATION_CONTROL3, URGENCY_WATERMARK_MASK, mask_sh),\
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+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
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+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
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+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
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+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
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+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
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+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
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+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
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+
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+#define MI_DCE6_MASK_SH_LIST(mask_sh)\
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+	MI_DCP_MASK_SH_LIST_DCE6(mask_sh, ),\
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+	MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, ),\
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+	MI_DMIF_PG_MASK_SH_DCE6(mask_sh, ),\
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+	MI_GFX6_TILE_MASK_SH_LIST(mask_sh, )
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+#endif
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 #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
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 	SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
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@@ -345,6 +438,16 @@
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 	const struct dce_mem_input_shift *mi_shift,
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 	const struct dce_mem_input_mask *mi_mask);
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+void dce60_mem_input_construct(
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+	struct dce_mem_input *dce_mi,
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+	struct dc_context *ctx,
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+	int inst,
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+	const struct dce_mem_input_registers *regs,
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+	const struct dce_mem_input_shift *mi_shift,
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+	const struct dce_mem_input_mask *mi_mask);
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+#endif
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+
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 void dce112_mem_input_construct(
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 	struct dce_mem_input *dce_mi,
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 	struct dc_context *ctx,