disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
..
..
@@ -38,7 +38,8 @@
38
38
 
39
39
 #define AUX_REG_LIST(id)\
40
40
 	SRI(AUX_CONTROL, DP_AUX, id), \
41
-	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
41
+	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
42
+	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
42
43
 
43
44
 #define HPD_REG_LIST(id)\
44
45
 	SRI(DC_HPD_CONTROL, HPD, id)
..
..
@@ -75,6 +76,34 @@
75
76
 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
76
77
 	SR(DCI_MEM_PWR_STATUS)
77
78
 
79
+#if defined(CONFIG_DRM_AMD_DC_SI)
80
+#define LE_DCE60_REG_LIST(id)\
81
+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
82
+	SR(DMCU_RAM_ACCESS_CTRL), \
83
+	SR(DMCU_IRAM_RD_CTRL), \
84
+	SR(DMCU_IRAM_RD_DATA), \
85
+	SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
86
+	SRI(DIG_BE_CNTL, DIG, id), \
87
+	SRI(DIG_BE_EN_CNTL, DIG, id), \
88
+	SRI(DP_CONFIG, DP, id), \
89
+	SRI(DP_DPHY_CNTL, DP, id), \
90
+	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
91
+	SRI(DP_DPHY_SYM0, DP, id), \
92
+	SRI(DP_DPHY_SYM1, DP, id), \
93
+	SRI(DP_DPHY_SYM2, DP, id), \
94
+	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
95
+	SRI(DP_LINK_CNTL, DP, id), \
96
+	SRI(DP_LINK_FRAMING_CNTL, DP, id), \
97
+	SRI(DP_MSE_SAT0, DP, id), \
98
+	SRI(DP_MSE_SAT1, DP, id), \
99
+	SRI(DP_MSE_SAT2, DP, id), \
100
+	SRI(DP_MSE_SAT_UPDATE, DP, id), \
101
+	SRI(DP_SEC_CNTL, DP, id), \
102
+	SRI(DP_VID_STREAM_CNTL, DP, id), \
103
+	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
104
+	SRI(DP_SEC_CNTL1, DP, id)
105
+#endif
106
+
78
107
 #define LE_DCE80_REG_LIST(id)\
79
108
 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
80
109
 	LE_COMMON_REG_LIST_BASE(id)
..
..
@@ -107,6 +136,7 @@
107
136
 struct dce110_link_enc_aux_registers {
108
137
 	uint32_t AUX_CONTROL;
109
138
 	uint32_t AUX_DPHY_RX_CONTROL0;
139
+	uint32_t AUX_DPHY_RX_CONTROL1;
110
140
 };
111
141
 
112
142
 struct dce110_link_enc_hpd_registers {
..
..
@@ -169,6 +199,16 @@
169
199
 	const struct dce110_link_enc_aux_registers *aux_regs,
170
200
 	const struct dce110_link_enc_hpd_registers *hpd_regs);
171
201
 
202
+#if defined(CONFIG_DRM_AMD_DC_SI)
203
+void dce60_link_encoder_construct(
204
+	struct dce110_link_encoder *enc110,
205
+	const struct encoder_init_data *init_data,
206
+	const struct encoder_feature_support *enc_features,
207
+	const struct dce110_link_enc_registers *link_regs,
208
+	const struct dce110_link_enc_aux_registers *aux_regs,
209
+	const struct dce110_link_enc_hpd_registers *hpd_regs);
210
+#endif
211
+
172
212
 bool dce110_link_encoder_validate_dvi_output(
173
213
 	const struct dce110_link_encoder *enc110,
174
214
 	enum signal_type connector_signal,
..
..
@@ -225,6 +265,12 @@
225
265
 	const struct dc_link_settings *link_settings,
226
266
 	enum clock_source_id clock_source);
227
267
 
268
+/* enables LVDS PHY output */
269
+void dce110_link_encoder_enable_lvds_output(
270
+	struct link_encoder *enc,
271
+	enum clock_source_id clock_source,
272
+	uint32_t pixel_clock);
273
+
228
274
 /* disable PHY output */
229
275
 void dce110_link_encoder_disable_output(
230
276
 	struct link_encoder *enc,
..
..
@@ -249,6 +295,8 @@
249
295
 	enum engine_id engine,
250
296
 	bool connect);
251
297
 
298
+unsigned int dce110_get_dig_frontend(struct link_encoder *enc);
299
+
252
300
 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
253
301
 	struct link_encoder *enc,
254
302
 	uint32_t index);
..
..
@@ -265,4 +313,7 @@
265
313
 
266
314
 bool dce110_is_dig_enabled(struct link_encoder *enc);
267
315
 
316
+void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,
317
+	struct dc_link_settings *link_settings);
318
+
268
319
 #endif /* __DC_LINK_ENCODER__DCE110_H__ */