forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
....@@ -25,11 +25,7 @@
2525 #ifndef __DCE_HWSEQ_H__
2626 #define __DCE_HWSEQ_H__
2727 
28
-#include "hw_sequencer.h"
29
-
30
-#define BL_REG_LIST()\
31
-	SR(LVTMA_PWRSEQ_CNTL), \
32
-	SR(LVTMA_PWRSEQ_STATE)
28
+#include "dc_types.h"
3329 
3430 #define HWSEQ_DCEF_REG_LIST_DCE8() \
3531 	.DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
....@@ -62,6 +58,10 @@
6258 	SRII(BLND_CONTROL, BLND, 4), \
6359 	SRII(BLND_CONTROL, BLND, 5)
6460 
61
+#define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \
62
+	SRII(PIXEL_RATE_CNTL, blk, inst), \
63
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst)
64
+
6565 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
6666 	SRII(PIXEL_RATE_CNTL, blk, 0), \
6767 	SRII(PIXEL_RATE_CNTL, blk, 1), \
....@@ -78,6 +78,24 @@
7878 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
7979 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
8080 
81
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
82
+#define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \
83
+	SRII(PIXEL_RATE_CNTL, blk, 0), \
84
+	SRII(PIXEL_RATE_CNTL, blk, 1),\
85
+	SRII(PIXEL_RATE_CNTL, blk, 2),\
86
+	SRII(PIXEL_RATE_CNTL, blk, 3), \
87
+	SRII(PIXEL_RATE_CNTL, blk, 4), \
88
+	SRII(PIXEL_RATE_CNTL, blk, 5)
89
+
90
+#define HWSEQ_PHYPLL_REG_LIST_3(blk) \
91
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
92
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
93
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
94
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
95
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
96
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
97
+#endif
98
+
8199 #define HWSEQ_DCE11_REG_LIST_BASE() \
82100 	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
83101 	SR(DCFEV_CLOCK_CONTROL), \
....@@ -90,20 +108,23 @@
90108 	SRII(BLND_CONTROL, BLND, 0),\
91109 	SRII(BLND_CONTROL, BLND, 1),\
92110 	SR(BLNDV_CONTROL),\
93
-	HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
94
-	BL_REG_LIST()
111
+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
112
+
113
+#if defined(CONFIG_DRM_AMD_DC_SI)
114
+#define HWSEQ_DCE6_REG_LIST() \
115
+	HWSEQ_DCEF_REG_LIST_DCE8(), \
116
+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
117
+#endif
95118 
96119 #define HWSEQ_DCE8_REG_LIST() \
97120 	HWSEQ_DCEF_REG_LIST_DCE8(), \
98121 	HWSEQ_BLND_REG_LIST(), \
99
-	HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
100
-	BL_REG_LIST()
122
+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
101123 
102124 #define HWSEQ_DCE10_REG_LIST() \
103125 	HWSEQ_DCEF_REG_LIST(), \
104126 	HWSEQ_BLND_REG_LIST(), \
105
-	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
106
-	BL_REG_LIST()
127
+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
107128 
108129 #define HWSEQ_ST_REG_LIST() \
109130 	HWSEQ_DCE11_REG_LIST_BASE(), \
....@@ -130,14 +151,16 @@
130151 	SR(DCHUB_FB_LOCATION),\
131152 	SR(DCHUB_AGP_BASE),\
132153 	SR(DCHUB_AGP_BOT),\
133
-	SR(DCHUB_AGP_TOP), \
134
-	BL_REG_LIST()
154
+	SR(DCHUB_AGP_TOP)
155
+
156
+#define HWSEQ_VG20_REG_LIST() \
157
+	HWSEQ_DCE120_REG_LIST(),\
158
+	MMHUB_SR(MC_VM_XGMI_LFB_CNTL)
135159 
136160 #define HWSEQ_DCE112_REG_LIST() \
137161 	HWSEQ_DCE10_REG_LIST(), \
138162 	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
139
-	HWSEQ_PHYPLL_REG_LIST(CRTC), \
140
-	BL_REG_LIST()
163
+	HWSEQ_PHYPLL_REG_LIST(CRTC)
141164 
142165 #define HWSEQ_DCN_REG_LIST()\
143166 	SR(REFCLK_CNTL), \
....@@ -147,7 +170,10 @@
147170 	SR(DCCG_GATE_DISABLE_CNTL2), \
148171 	SR(DCFCLK_CNTL),\
149172 	SR(DCFCLK_CNTL), \
150
-	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
173
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
174
+
175
+
176
+#define MMHUB_DCN_REG_LIST()\
151177 	/* todo:  get these from GVM instead of reading registers ourselves */\
152178 	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
153179 	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
....@@ -162,10 +188,14 @@
162188 	MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
163189 	MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
164190 
191
+
165192 #define HWSEQ_DCN1_REG_LIST()\
166193 	HWSEQ_DCN_REG_LIST(), \
167
-	HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
168
-	HWSEQ_PHYPLL_REG_LIST(OTG), \
194
+	MMHUB_DCN_REG_LIST(), \
195
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
196
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
197
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
198
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
169199 	SR(DCHUBBUB_SDPIF_FB_BASE),\
170200 	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
171201 	SR(DCHUBBUB_SDPIF_AGP_BASE),\
....@@ -192,15 +222,146 @@
192222 	SR(D3VGA_CONTROL), \
193223 	SR(D4VGA_CONTROL), \
194224 	SR(VGA_TEST_CONTROL), \
195
-	SR(DC_IP_REQUEST_CNTL), \
196
-	BL_REG_LIST()
225
+	SR(DC_IP_REQUEST_CNTL)
226
+
227
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
228
+#define HWSEQ_DCN30_REG_LIST()\
229
+	HWSEQ_DCN2_REG_LIST(),\
230
+	HWSEQ_DCN_REG_LIST(), \
231
+	HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
232
+	HWSEQ_PHYPLL_REG_LIST_3(OTG), \
233
+	SR(MICROSECOND_TIME_BASE_DIV), \
234
+	SR(MILLISECOND_TIME_BASE_DIV), \
235
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
236
+	SR(RBBMIF_TIMEOUT_DIS), \
237
+	SR(RBBMIF_TIMEOUT_DIS_2), \
238
+	SR(DCHUBBUB_CRC_CTRL), \
239
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
240
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
241
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
242
+	SR(MPC_CRC_CTRL), \
243
+	SR(MPC_CRC_RESULT_GB), \
244
+	SR(MPC_CRC_RESULT_C), \
245
+	SR(MPC_CRC_RESULT_AR), \
246
+	SR(AZALIA_AUDIO_DTO), \
247
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
248
+#endif
249
+#define HWSEQ_DCN2_REG_LIST()\
250
+	HWSEQ_DCN_REG_LIST(), \
251
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
252
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
253
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
254
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
255
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
256
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \
257
+	SR(MICROSECOND_TIME_BASE_DIV), \
258
+	SR(MILLISECOND_TIME_BASE_DIV), \
259
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
260
+	SR(RBBMIF_TIMEOUT_DIS), \
261
+	SR(RBBMIF_TIMEOUT_DIS_2), \
262
+	SR(DCHUBBUB_CRC_CTRL), \
263
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
264
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
265
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
266
+	SR(MPC_CRC_CTRL), \
267
+	SR(MPC_CRC_RESULT_GB), \
268
+	SR(MPC_CRC_RESULT_C), \
269
+	SR(MPC_CRC_RESULT_AR), \
270
+	SR(DOMAIN0_PG_CONFIG), \
271
+	SR(DOMAIN1_PG_CONFIG), \
272
+	SR(DOMAIN2_PG_CONFIG), \
273
+	SR(DOMAIN3_PG_CONFIG), \
274
+	SR(DOMAIN4_PG_CONFIG), \
275
+	SR(DOMAIN5_PG_CONFIG), \
276
+	SR(DOMAIN6_PG_CONFIG), \
277
+	SR(DOMAIN7_PG_CONFIG), \
278
+	SR(DOMAIN8_PG_CONFIG), \
279
+	SR(DOMAIN9_PG_CONFIG), \
280
+/*	SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\
281
+/*	SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\
282
+	SR(DOMAIN16_PG_CONFIG), \
283
+	SR(DOMAIN17_PG_CONFIG), \
284
+	SR(DOMAIN18_PG_CONFIG), \
285
+	SR(DOMAIN19_PG_CONFIG), \
286
+	SR(DOMAIN20_PG_CONFIG), \
287
+	SR(DOMAIN21_PG_CONFIG), \
288
+	SR(DOMAIN0_PG_STATUS), \
289
+	SR(DOMAIN1_PG_STATUS), \
290
+	SR(DOMAIN2_PG_STATUS), \
291
+	SR(DOMAIN3_PG_STATUS), \
292
+	SR(DOMAIN4_PG_STATUS), \
293
+	SR(DOMAIN5_PG_STATUS), \
294
+	SR(DOMAIN6_PG_STATUS), \
295
+	SR(DOMAIN7_PG_STATUS), \
296
+	SR(DOMAIN8_PG_STATUS), \
297
+	SR(DOMAIN9_PG_STATUS), \
298
+	SR(DOMAIN10_PG_STATUS), \
299
+	SR(DOMAIN11_PG_STATUS), \
300
+	SR(DOMAIN16_PG_STATUS), \
301
+	SR(DOMAIN17_PG_STATUS), \
302
+	SR(DOMAIN18_PG_STATUS), \
303
+	SR(DOMAIN19_PG_STATUS), \
304
+	SR(DOMAIN20_PG_STATUS), \
305
+	SR(DOMAIN21_PG_STATUS), \
306
+	SR(D1VGA_CONTROL), \
307
+	SR(D2VGA_CONTROL), \
308
+	SR(D3VGA_CONTROL), \
309
+	SR(D4VGA_CONTROL), \
310
+	SR(D5VGA_CONTROL), \
311
+	SR(D6VGA_CONTROL), \
312
+	SR(DC_IP_REQUEST_CNTL)
313
+
314
+#define HWSEQ_DCN21_REG_LIST()\
315
+	HWSEQ_DCN_REG_LIST(), \
316
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
317
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
318
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
319
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
320
+	MMHUB_DCN_REG_LIST(), \
321
+	SR(MICROSECOND_TIME_BASE_DIV), \
322
+	SR(MILLISECOND_TIME_BASE_DIV), \
323
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
324
+	SR(RBBMIF_TIMEOUT_DIS), \
325
+	SR(RBBMIF_TIMEOUT_DIS_2), \
326
+	SR(DCHUBBUB_CRC_CTRL), \
327
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
328
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
329
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
330
+	SR(MPC_CRC_CTRL), \
331
+	SR(MPC_CRC_RESULT_GB), \
332
+	SR(MPC_CRC_RESULT_C), \
333
+	SR(MPC_CRC_RESULT_AR), \
334
+	SR(DOMAIN0_PG_CONFIG), \
335
+	SR(DOMAIN1_PG_CONFIG), \
336
+	SR(DOMAIN2_PG_CONFIG), \
337
+	SR(DOMAIN3_PG_CONFIG), \
338
+	SR(DOMAIN4_PG_CONFIG), \
339
+	SR(DOMAIN5_PG_CONFIG), \
340
+	SR(DOMAIN6_PG_CONFIG), \
341
+	SR(DOMAIN7_PG_CONFIG), \
342
+	SR(DOMAIN16_PG_CONFIG), \
343
+	SR(DOMAIN17_PG_CONFIG), \
344
+	SR(DOMAIN18_PG_CONFIG), \
345
+	SR(DOMAIN0_PG_STATUS), \
346
+	SR(DOMAIN1_PG_STATUS), \
347
+	SR(DOMAIN2_PG_STATUS), \
348
+	SR(DOMAIN3_PG_STATUS), \
349
+	SR(DOMAIN4_PG_STATUS), \
350
+	SR(DOMAIN5_PG_STATUS), \
351
+	SR(DOMAIN6_PG_STATUS), \
352
+	SR(DOMAIN7_PG_STATUS), \
353
+	SR(DOMAIN16_PG_STATUS), \
354
+	SR(DOMAIN17_PG_STATUS), \
355
+	SR(DOMAIN18_PG_STATUS), \
356
+	SR(D1VGA_CONTROL), \
357
+	SR(D2VGA_CONTROL), \
358
+	SR(D3VGA_CONTROL), \
359
+	SR(D4VGA_CONTROL), \
360
+	SR(D5VGA_CONTROL), \
361
+	SR(D6VGA_CONTROL), \
362
+	SR(DC_IP_REQUEST_CNTL)
197363 
198364 struct dce_hwseq_registers {
199
-
200
-		/* Backlight registers */
201
-	uint32_t LVTMA_PWRSEQ_CNTL;
202
-	uint32_t LVTMA_PWRSEQ_STATE;
203
-
204365 	uint32_t DCFE_CLOCK_CONTROL[6];
205366 	uint32_t DCFEV_CLOCK_CONTROL;
206367 	uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
....@@ -233,6 +394,16 @@
233394 	uint32_t DOMAIN5_PG_CONFIG;
234395 	uint32_t DOMAIN6_PG_CONFIG;
235396 	uint32_t DOMAIN7_PG_CONFIG;
397
+	uint32_t DOMAIN8_PG_CONFIG;
398
+	uint32_t DOMAIN9_PG_CONFIG;
399
+	uint32_t DOMAIN10_PG_CONFIG;
400
+	uint32_t DOMAIN11_PG_CONFIG;
401
+	uint32_t DOMAIN16_PG_CONFIG;
402
+	uint32_t DOMAIN17_PG_CONFIG;
403
+	uint32_t DOMAIN18_PG_CONFIG;
404
+	uint32_t DOMAIN19_PG_CONFIG;
405
+	uint32_t DOMAIN20_PG_CONFIG;
406
+	uint32_t DOMAIN21_PG_CONFIG;
236407 	uint32_t DOMAIN0_PG_STATUS;
237408 	uint32_t DOMAIN1_PG_STATUS;
238409 	uint32_t DOMAIN2_PG_STATUS;
....@@ -241,6 +412,16 @@
241412 	uint32_t DOMAIN5_PG_STATUS;
242413 	uint32_t DOMAIN6_PG_STATUS;
243414 	uint32_t DOMAIN7_PG_STATUS;
415
+	uint32_t DOMAIN8_PG_STATUS;
416
+	uint32_t DOMAIN9_PG_STATUS;
417
+	uint32_t DOMAIN10_PG_STATUS;
418
+	uint32_t DOMAIN11_PG_STATUS;
419
+	uint32_t DOMAIN16_PG_STATUS;
420
+	uint32_t DOMAIN17_PG_STATUS;
421
+	uint32_t DOMAIN18_PG_STATUS;
422
+	uint32_t DOMAIN19_PG_STATUS;
423
+	uint32_t DOMAIN20_PG_STATUS;
424
+	uint32_t DOMAIN21_PG_STATUS;
244425 	uint32_t DIO_MEM_PWR_CTRL;
245426 	uint32_t DCCG_GATE_DISABLE_CNTL;
246427 	uint32_t DCCG_GATE_DISABLE_CNTL2;
....@@ -262,6 +443,8 @@
262443 	uint32_t D2VGA_CONTROL;
263444 	uint32_t D3VGA_CONTROL;
264445 	uint32_t D4VGA_CONTROL;
446
+	uint32_t D5VGA_CONTROL;
447
+	uint32_t D6VGA_CONTROL;
265448 	uint32_t VGA_TEST_CONTROL;
266449 	/* MMHUB registers. read only. temporary hack */
267450 	uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
....@@ -276,6 +459,7 @@
276459 	uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
277460 	uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
278461 	uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
462
+	uint32_t MC_VM_XGMI_LFB_CNTL;
279463 	uint32_t AZALIA_AUDIO_DTO;
280464 	uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
281465 };
....@@ -310,36 +494,32 @@
310494 	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
311495 	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
312496 
497
+#if defined(CONFIG_DRM_AMD_DC_SI)
498
+#define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\
499
+	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
500
+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
501
+#endif
502
+
313503 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
314504 	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
315505 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
316506 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
317507 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
318508 	HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
319
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
320
-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
321509 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
322510 
323511 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
324512 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
325513 	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
326
-	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \
327
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
328
-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
514
+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
329515 
330516 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
331517 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
332518 	SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
333
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
334
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
335
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
336
-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
337519 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
338520 
339521 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
340522 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
341
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
342
-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
343523 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
344524 
345525 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
....@@ -347,18 +527,19 @@
347527 	SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
348528 	SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
349529 	SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
350
-	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \
351
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
352
-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
530
+	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
353531 
354532 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
355533 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
356534 	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
357535 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
358536 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
359
-	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \
360
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
361
-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
537
+	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
538
+
539
+#define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\
540
+	HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
541
+	HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\
542
+	HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh)
362543 
363544 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
364545 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
....@@ -415,11 +596,112 @@
415596 	HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
416597 	HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
417598 	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
418
-	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
419
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
420
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \
421
-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \
422
-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
599
+	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
600
+
601
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
602
+#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
603
+	HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
604
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
605
+#endif
606
+
607
+#define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
608
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
609
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
610
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
611
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
612
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
613
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
614
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
615
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
616
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
617
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
618
+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
619
+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
620
+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
621
+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
622
+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
623
+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
624
+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
625
+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
626
+	HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \
627
+	HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \
628
+	HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \
629
+	HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \
630
+	HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \
631
+	HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \
632
+	HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \
633
+	HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \
634
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
635
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
636
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
637
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
638
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
639
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
640
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \
641
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \
642
+	HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \
643
+	HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \
644
+	HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \
645
+	HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \
646
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
647
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
648
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
649
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
650
+	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
651
+	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
652
+	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
653
+	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
654
+	HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \
655
+	HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \
656
+	HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \
657
+	HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \
658
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
659
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
660
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
661
+	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
662
+	HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
663
+	HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
664
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
665
+
666
+#define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
667
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
668
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
669
+	HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
670
+	HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
671
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
672
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
673
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
674
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
675
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
676
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
677
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
678
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
679
+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
680
+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
681
+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
682
+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
683
+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
684
+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
685
+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
686
+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
687
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
688
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
689
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
690
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
691
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
692
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
693
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
694
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
695
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
696
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
697
+	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
698
+	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
699
+	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
700
+	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
701
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
702
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
703
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
704
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
423705 
424706 #define HWSEQ_REG_FIELD_LIST(type) \
425707 	type DCFE_CLOCK_ENABLE; \
....@@ -448,12 +730,10 @@
448730 	type PHYSICAL_PAGE_NUMBER_MSB;\
449731 	type PHYSICAL_PAGE_NUMBER_LSB;\
450732 	type LOGICAL_ADDR; \
733
+	type PF_LFB_REGION;\
734
+	type PF_MAX_REGION;\
451735 	type ENABLE_L1_TLB;\
452
-	type SYSTEM_ACCESS_MODE;\
453
-	type LVTMA_BLON;\
454
-	type LVTMA_PWRSEQ_TARGET_STATE_R;\
455
-	type LVTMA_DIGON;\
456
-	type LVTMA_DIGON_OVRD;
736
+	type SYSTEM_ACCESS_MODE;
457737 
458738 #define HWSEQ_DCN_REG_FIELD_LIST(type) \
459739 	type HUBP_VTG_SEL; \
....@@ -489,6 +769,26 @@
489769 	type DOMAIN6_POWER_GATE; \
490770 	type DOMAIN7_POWER_FORCEON; \
491771 	type DOMAIN7_POWER_GATE; \
772
+	type DOMAIN8_POWER_FORCEON; \
773
+	type DOMAIN8_POWER_GATE; \
774
+	type DOMAIN9_POWER_FORCEON; \
775
+	type DOMAIN9_POWER_GATE; \
776
+	type DOMAIN10_POWER_FORCEON; \
777
+	type DOMAIN10_POWER_GATE; \
778
+	type DOMAIN11_POWER_FORCEON; \
779
+	type DOMAIN11_POWER_GATE; \
780
+	type DOMAIN16_POWER_FORCEON; \
781
+	type DOMAIN16_POWER_GATE; \
782
+	type DOMAIN17_POWER_FORCEON; \
783
+	type DOMAIN17_POWER_GATE; \
784
+	type DOMAIN18_POWER_FORCEON; \
785
+	type DOMAIN18_POWER_GATE; \
786
+	type DOMAIN19_POWER_FORCEON; \
787
+	type DOMAIN19_POWER_GATE; \
788
+	type DOMAIN20_POWER_FORCEON; \
789
+	type DOMAIN20_POWER_GATE; \
790
+	type DOMAIN21_POWER_FORCEON; \
791
+	type DOMAIN21_POWER_GATE; \
492792 	type DOMAIN0_PGFSM_PWR_STATUS; \
493793 	type DOMAIN1_PGFSM_PWR_STATUS; \
494794 	type DOMAIN2_PGFSM_PWR_STATUS; \
....@@ -497,6 +797,16 @@
497797 	type DOMAIN5_PGFSM_PWR_STATUS; \
498798 	type DOMAIN6_PGFSM_PWR_STATUS; \
499799 	type DOMAIN7_PGFSM_PWR_STATUS; \
800
+	type DOMAIN8_PGFSM_PWR_STATUS; \
801
+	type DOMAIN9_PGFSM_PWR_STATUS; \
802
+	type DOMAIN10_PGFSM_PWR_STATUS; \
803
+	type DOMAIN11_PGFSM_PWR_STATUS; \
804
+	type DOMAIN16_PGFSM_PWR_STATUS; \
805
+	type DOMAIN17_PGFSM_PWR_STATUS; \
806
+	type DOMAIN18_PGFSM_PWR_STATUS; \
807
+	type DOMAIN19_PGFSM_PWR_STATUS; \
808
+	type DOMAIN20_PGFSM_PWR_STATUS; \
809
+	type DOMAIN21_PGFSM_PWR_STATUS; \
500810 	type DCFCLK_GATE_DIS; \
501811 	type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
502812 	type VGA_TEST_ENABLE; \
....@@ -524,6 +834,10 @@
524834 	BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
525835 };
526836 
837
+struct dce_hwseq;
838
+struct pipe_ctx;
839
+struct clock_source;
840
+
527841 void dce_enable_fe_clock(struct dce_hwseq *hwss,
528842 		unsigned int inst, bool enable);
529843 
....@@ -534,6 +848,12 @@
534848 void dce_set_blender_mode(struct dce_hwseq *hws,
535849 	unsigned int blnd_inst, enum blnd_mode mode);
536850 
851
+#if defined(CONFIG_DRM_AMD_DC_SI)
852
+void dce60_pipe_control_lock(struct dc *dc,
853
+		struct pipe_ctx *pipe,
854
+		bool lock);
855
+#endif
856
+
537857 void dce_clock_gating_power_up(struct dce_hwseq *hws,
538858 		bool enable);
539859