disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
..
..
@@ -46,6 +46,24 @@
46
46
 	SR(SMU_INTERRUPT_CONTROL), \
47
47
 	SR(DC_DMCU_SCRATCH)
48
48
 
49
+#if defined(CONFIG_DRM_AMD_DC_SI)
50
+#define DMCU_DCE60_REG_LIST() \
51
+	SR(DMCU_CTRL), \
52
+	SR(DMCU_STATUS), \
53
+	SR(DMCU_RAM_ACCESS_CTRL), \
54
+	SR(DMCU_IRAM_WR_CTRL), \
55
+	SR(DMCU_IRAM_WR_DATA), \
56
+	SR(MASTER_COMM_DATA_REG1), \
57
+	SR(MASTER_COMM_DATA_REG2), \
58
+	SR(MASTER_COMM_DATA_REG3), \
59
+	SR(MASTER_COMM_CMD_REG), \
60
+	SR(MASTER_COMM_CNTL_REG), \
61
+	SR(DMCU_IRAM_RD_CTRL), \
62
+	SR(DMCU_IRAM_RD_DATA), \
63
+	SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
64
+	SR(DC_DMCU_SCRATCH)
65
+#endif
66
+
49
67
 #define DMCU_DCE80_REG_LIST() \
50
68
 	SR(DMCU_CTRL), \
51
69
 	SR(DMCU_STATUS), \
..
..
@@ -70,6 +88,10 @@
70
88
 #define DMCU_DCN10_REG_LIST()\
71
89
 	DMCU_COMMON_REG_LIST_DCE_BASE(), \
72
90
 	SR(DMU_MEM_PWR_CNTL)
91
+
92
+#define DMCU_DCN20_REG_LIST()\
93
+	DMCU_DCN10_REG_LIST(), \
94
+	SR(DMCUB_SCRATCH15)
73
95
 
74
96
 #define DMCU_SF(reg_name, field_name, post_fix)\
75
97
 	.field_name = reg_name ## __ ## field_name ## post_fix
..
..
@@ -99,6 +121,25 @@
99
121
 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
100
122
 			STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
101
123
 	DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
124
+
125
+#if defined(CONFIG_DRM_AMD_DC_SI)
126
+#define DMCU_MASK_SH_LIST_DCE60(mask_sh) \
127
+	DMCU_SF(DMCU_CTRL, \
128
+			DMCU_ENABLE, mask_sh), \
129
+	DMCU_SF(DMCU_STATUS, \
130
+			UC_IN_STOP_MODE, mask_sh), \
131
+	DMCU_SF(DMCU_STATUS, \
132
+			UC_IN_RESET, mask_sh), \
133
+	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
134
+			IRAM_HOST_ACCESS_EN, mask_sh), \
135
+	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
136
+			IRAM_WR_ADDR_AUTO_INC, mask_sh), \
137
+	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
138
+			IRAM_RD_ADDR_AUTO_INC, mask_sh), \
139
+	DMCU_SF(MASTER_COMM_CMD_REG, \
140
+			MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
141
+	DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
142
+#endif
102
143
 
103
144
 #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
104
145
 	DMCU_SF(DMCU_CTRL, \
..
..
@@ -175,6 +216,7 @@
175
216
 	uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
176
217
 	uint32_t SMU_INTERRUPT_CONTROL;
177
218
 	uint32_t DC_DMCU_SCRATCH;
219
+	uint32_t DMCUB_SCRATCH15;
178
220
 };
179
221
 
180
222
 struct dce_dmcu {
..
..
@@ -199,16 +241,16 @@
199
241
  ******************************************************************/
200
242
 union dce_dmcu_psr_config_data_reg1 {
201
243
 	struct {
202
-		unsigned int timehyst_frames:8;    /*[7:0]*/
203
-		unsigned int hyst_lines:7;         /*[14:8]*/
204
-		unsigned int rfb_update_auto_en:1; /*[15:15]*/
205
-		unsigned int dp_port_num:3;        /*[18:16]*/
206
-		unsigned int dcp_sel:3;            /*[21:19]*/
207
-		unsigned int phy_type:1;           /*[22:22]*/
208
-		unsigned int frame_cap_ind:1;      /*[23:23]*/
209
-		unsigned int aux_chan:3;           /*[26:24]*/
210
-		unsigned int aux_repeat:4;         /*[30:27]*/
211
-		unsigned int reserved:1;           /*[31:31]*/
244
+		unsigned int timehyst_frames:8;                  /*[7:0]*/
245
+		unsigned int hyst_lines:7;                       /*[14:8]*/
246
+		unsigned int rfb_update_auto_en:1;               /*[15:15]*/
247
+		unsigned int dp_port_num:3;                      /*[18:16]*/
248
+		unsigned int dcp_sel:3;                          /*[21:19]*/
249
+		unsigned int phy_type:1;                         /*[22:22]*/
250
+		unsigned int frame_cap_ind:1;                    /*[23:23]*/
251
+		unsigned int aux_chan:3;                         /*[26:24]*/
252
+		unsigned int aux_repeat:4;                       /*[30:27]*/
253
+		unsigned int allow_smu_optimizations:1;         /*[31:31]*/
212
254
 	} bits;
213
255
 	unsigned int u32All;
214
256
 };
..
..
@@ -236,7 +278,7 @@
236
278
 	struct {
237
279
 		unsigned int psr_level:16;      /*[15:0]*/
238
280
 		unsigned int link_rate:4;       /*[19:16]*/
239
-		unsigned int reserved:12;       /*[31:20]*/
281
+		unsigned int reserved:12;        /*[31:20]*/
240
282
 	} bits;
241
283
 	unsigned int u32All;
242
284
 };
..
..
@@ -261,6 +303,20 @@
261
303
 	const struct dce_dmcu_shift *dmcu_shift,
262
304
 	const struct dce_dmcu_mask *dmcu_mask);
263
305
 
306
+struct dmcu *dcn20_dmcu_create(
307
+	struct dc_context *ctx,
308
+	const struct dce_dmcu_registers *regs,
309
+	const struct dce_dmcu_shift *dmcu_shift,
310
+	const struct dce_dmcu_mask *dmcu_mask);
311
+
312
+struct dmcu *dcn21_dmcu_create(
313
+	struct dc_context *ctx,
314
+	const struct dce_dmcu_registers *regs,
315
+	const struct dce_dmcu_shift *dmcu_shift,
316
+	const struct dce_dmcu_mask *dmcu_mask);
317
+
264
318
 void dce_dmcu_destroy(struct dmcu **dmcu);
265
319
 
320
+static const uint32_t abm_gain_stepsize = 0x0060;
321
+
266
322
 #endif /* _DCE_ABM_H_ */