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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
....@@ -25,7 +25,19 @@
2525 
2626 #ifndef __DAL_AUX_ENGINE_DCE110_H__
2727 #define __DAL_AUX_ENGINE_DCE110_H__
28
-#include "aux_engine.h"
28
+
29
+#include "i2caux_interface.h"
30
+#include "inc/hw/aux_engine.h"
31
+
32
+
33
+#define AUX_COMMON_REG_LIST0(id)\
34
+	SRI(AUX_CONTROL, DP_AUX, id), \
35
+	SRI(AUX_ARB_CONTROL, DP_AUX, id), \
36
+	SRI(AUX_SW_DATA, DP_AUX, id), \
37
+	SRI(AUX_SW_CONTROL, DP_AUX, id), \
38
+	SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
39
+	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
40
+	SRI(AUX_SW_STATUS, DP_AUX, id)
2941 
3042 #define AUX_COMMON_REG_LIST(id)\
3143 	SRI(AUX_CONTROL, DP_AUX, id), \
....@@ -43,12 +55,162 @@
4355 	uint32_t AUX_SW_DATA;
4456 	uint32_t AUX_SW_CONTROL;
4557 	uint32_t AUX_INTERRUPT_CONTROL;
58
+	uint32_t AUX_DPHY_RX_CONTROL1;
4659 	uint32_t AUX_SW_STATUS;
4760 	uint32_t AUXN_IMPCAL;
4861 	uint32_t AUXP_IMPCAL;
4962 
5063 	uint32_t AUX_RESET_MASK;
5164 };
65
+
66
+#define DCE_AUX_REG_FIELD_LIST(type)\
67
+	type AUX_EN;\
68
+	type AUX_RESET;\
69
+	type AUX_RESET_DONE;\
70
+	type AUX_REG_RW_CNTL_STATUS;\
71
+	type AUX_SW_USE_AUX_REG_REQ;\
72
+	type AUX_SW_DONE_USING_AUX_REG;\
73
+	type AUX_SW_AUTOINCREMENT_DISABLE;\
74
+	type AUX_SW_DATA_RW;\
75
+	type AUX_SW_INDEX;\
76
+	type AUX_SW_GO;\
77
+	type AUX_SW_DATA;\
78
+	type AUX_SW_REPLY_BYTE_COUNT;\
79
+	type AUX_SW_DONE;\
80
+	type AUX_SW_DONE_ACK;\
81
+	type AUXN_IMPCAL_ENABLE;\
82
+	type AUXP_IMPCAL_ENABLE;\
83
+	type AUXN_IMPCAL_OVERRIDE_ENABLE;\
84
+	type AUXP_IMPCAL_OVERRIDE_ENABLE;\
85
+	type AUX_RX_TIMEOUT_LEN;\
86
+	type AUX_RX_TIMEOUT_LEN_MUL;\
87
+	type AUXN_CALOUT_ERROR_AK;\
88
+	type AUXP_CALOUT_ERROR_AK;\
89
+	type AUX_SW_START_DELAY;\
90
+	type AUX_SW_WR_BYTES
91
+
92
+#define DCE10_AUX_MASK_SH_LIST(mask_sh)\
93
+	AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
94
+	AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
95
+	AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
96
+	AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
97
+	AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
98
+	AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
99
+	AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
100
+	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
101
+	AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
102
+	AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
103
+	AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
104
+	AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
105
+	AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
106
+	AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
107
+	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
108
+	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
109
+	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
110
+	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
111
+	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
112
+	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
113
+
114
+#define DCE_AUX_MASK_SH_LIST(mask_sh)\
115
+	AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
116
+	AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
117
+	AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
118
+	AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
119
+	AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
120
+	AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
121
+	AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
122
+	AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
123
+	AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
124
+	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
125
+	AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
126
+	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
127
+	AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
128
+	AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
129
+	AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
130
+	AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
131
+	AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
132
+	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
133
+	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
134
+	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
135
+	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
136
+	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
137
+	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
138
+
139
+#define DCE12_AUX_MASK_SH_LIST(mask_sh)\
140
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
141
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
142
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
143
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
144
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
145
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
146
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
147
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
148
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
149
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
150
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
151
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
152
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
153
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
154
+	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
155
+	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
156
+	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
157
+	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
158
+	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
159
+	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
160
+	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
161
+	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
162
+	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
163
+
164
+/* DCN10 MASK */
165
+#define DCN10_AUX_MASK_SH_LIST(mask_sh)\
166
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
167
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
168
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
169
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
170
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
171
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
172
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
173
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
174
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
175
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
176
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
177
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
178
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
179
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
180
+	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
181
+	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
182
+	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
183
+	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
184
+	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
185
+	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
186
+	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
187
+	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
188
+	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
189
+
190
+/* for all other DCN */
191
+#define DCN_AUX_MASK_SH_LIST(mask_sh)\
192
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
193
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
194
+	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
195
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
196
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
197
+	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
198
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
199
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
200
+	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
201
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
202
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
203
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
204
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
205
+	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
206
+	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
207
+	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
208
+	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
209
+	AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
210
+	AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)
211
+
212
+#define AUX_SF(reg_name, field_name, post_fix)\
213
+	.field_name = reg_name ## __ ## field_name ## post_fix
52214 
53215 enum {	/* This is the timeout as defined in DP 1.2a,
54216 	 * 2.3.4 "Detailed uPacket TX AUX CH State Description".
....@@ -75,18 +237,44 @@
75237 	 */
76238 	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6
77239 };
240
+
241
+struct dce_aux {
242
+	uint32_t inst;
243
+	struct ddc *ddc;
244
+	struct dc_context *ctx;
245
+	/* following values are expressed in milliseconds */
246
+	uint32_t delay;
247
+	uint32_t max_defer_write_retry;
248
+
249
+	bool acquire_reset;
250
+	struct dce_aux_funcs *funcs;
251
+};
252
+
253
+struct dce110_aux_registers_mask {
254
+	DCE_AUX_REG_FIELD_LIST(uint32_t);
255
+};
256
+
257
+struct dce110_aux_registers_shift {
258
+	DCE_AUX_REG_FIELD_LIST(uint8_t);
259
+};
260
+
261
+
78262 struct aux_engine_dce110 {
79
-	struct aux_engine base;
263
+	struct dce_aux base;
80264 	const struct dce110_aux_registers *regs;
265
+	const struct dce110_aux_registers_mask *mask;
266
+	const struct dce110_aux_registers_shift *shift;
81267 	struct {
82268 		uint32_t aux_control;
83269 		uint32_t aux_arb_control;
84270 		uint32_t aux_sw_data;
85271 		uint32_t aux_sw_control;
86272 		uint32_t aux_interrupt_control;
273
+		uint32_t aux_dphy_rx_control1;
274
+		uint32_t aux_dphy_rx_control0;
87275 		uint32_t aux_sw_status;
88276 	} addr;
89
-	uint32_t timeout_period;
277
+	uint32_t polling_timeout_period;
90278 };
91279 
92280 struct aux_engine_dce110_init_data {
....@@ -96,16 +284,35 @@
96284 	const struct dce110_aux_registers *regs;
97285 };
98286 
99
-struct aux_engine *dce110_aux_engine_construct(
100
-		struct aux_engine_dce110 *aux_engine110,
287
+struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
101288 		struct dc_context *ctx,
102289 		uint32_t inst,
103290 		uint32_t timeout_period,
104
-		const struct dce110_aux_registers *regs);
291
+		const struct dce110_aux_registers *regs,
105292 
106
-void dce110_engine_destroy(struct aux_engine **engine);
293
+		const struct dce110_aux_registers_mask *mask,
294
+		const struct dce110_aux_registers_shift *shift,
295
+		bool is_ext_aux_timeout_configurable);
296
+
297
+void dce110_engine_destroy(struct dce_aux **engine);
107298 
108299 bool dce110_aux_engine_acquire(
109
-	struct aux_engine *aux_engine,
300
+	struct dce_aux *aux_engine,
110301 	struct ddc *ddc);
302
+
303
+int dce_aux_transfer_raw(struct ddc_service *ddc,
304
+		struct aux_payload *cmd,
305
+		enum aux_channel_operation_result *operation_result);
306
+
307
+bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
308
+		struct aux_payload *cmd);
309
+
310
+struct dce_aux_funcs {
311
+	uint32_t (*configure_timeout)
312
+		(struct ddc_service *ddc,
313
+		 uint32_t timeout);
314
+	void (*destroy)
315
+		(struct aux_engine **ptr);
316
+};
317
+
111318 #endif