disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
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..
@@ -49,6 +49,8 @@
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 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
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 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
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 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
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+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
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+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
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 		SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
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 		SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
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 		SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
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@@ -62,6 +64,20 @@
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 		SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
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 		SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define AUD_DCE60_MASK_SH_LIST(mask_sh)\
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+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
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+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
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+		SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
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+		SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
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+		SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
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+		SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
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+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
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+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
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+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh), \
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+		SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
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+		SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
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+#endif
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 struct dce_audio_registers {
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 	uint32_t AZALIA_F0_CODEC_ENDPOINT_INDEX;
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@@ -95,9 +111,11 @@
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 	uint8_t DCCG_AUDIO_DTO1_MODULE;
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 	uint8_t DCCG_AUDIO_DTO1_PHASE;
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 	uint8_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
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+	uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
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+	uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
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 };
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-struct dce_aduio_mask {
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+struct dce_audio_mask {
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 	uint32_t AZALIA_ENDPOINT_REG_INDEX;
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 	uint32_t AZALIA_ENDPOINT_REG_DATA;
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..
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@@ -112,13 +130,16 @@
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 	uint32_t DCCG_AUDIO_DTO1_MODULE;
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 	uint32_t DCCG_AUDIO_DTO1_PHASE;
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 	uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
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+	uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
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+	uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
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+
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 };
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 struct dce_audio {
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 	struct audio base;
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 	const struct dce_audio_registers *regs;
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 	const struct dce_audio_shift *shifts;
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-	const struct dce_aduio_mask *masks;
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+	const struct dce_audio_mask *masks;
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 };
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 struct audio *dce_audio_create(
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@@ -126,7 +147,16 @@
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 		unsigned int inst,
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 		const struct dce_audio_registers *reg,
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 		const struct dce_audio_shift *shifts,
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-		const struct dce_aduio_mask *masks);
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+		const struct dce_audio_mask *masks);
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+
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+struct audio *dce60_audio_create(
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+		struct dc_context *ctx,
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+		unsigned int inst,
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+		const struct dce_audio_registers *reg,
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+		const struct dce_audio_shift *shifts,
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+		const struct dce_audio_mask *masks);
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+#endif
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 void dce_aud_destroy(struct audio **audio);
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