~hc/RK356X_SDK_RELEASE.git

..	..	@@ -29,6 +29,9 @@
29	29	#include "dc_types.h"
30	30	#include "grph_object_defs.h"
31	31	#include "logger_types.h"
	32	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	33	+#include "hdcp_types.h"
	34	+#endif
32	35	#include "gpio_types.h"
33	36	#include "link_service_types.h"
34	37	#include "grph_object_ctrl_defs.h"
..	..	@@ -36,28 +39,109 @@
36	39
37	40	#include "inc/hw_sequencer.h"
38	41	#include "inc/compressor.h"
	42	+#include "inc/hw/dmcu.h"
39	43	#include "dml/display_mode_lib.h"
40	44
41		-#define DC_VER "3.1.59"
	45	+#define DC_VER "3.2.104"
42	46
43	47	#define MAX_SURFACES 3
	48	+#define MAX_PLANES 6
44	49	#define MAX_STREAMS 6
45	50	#define MAX_SINKS_PER_LINK 4
46		-
47	51
48	52	/*******************************************************************************
49	53	* Display Core Interfaces
50	54	******************************************************************************/
51		-struct dmcu_version {
52		- unsigned int date;
53		- unsigned int month;
54		- unsigned int year;
55		- unsigned int interface_version;
56		-};
57		-
58	55	struct dc_versions {
59	56	const char *dc_ver;
60	57	struct dmcu_version dmcu_version;
	58	+};
	59	+
	60	+enum dp_protocol_version {
	61	+ DP_VERSION_1_4,
	62	+};
	63	+
	64	+enum dc_plane_type {
	65	+ DC_PLANE_TYPE_INVALID,
	66	+ DC_PLANE_TYPE_DCE_RGB,
	67	+ DC_PLANE_TYPE_DCE_UNDERLAY,
	68	+ DC_PLANE_TYPE_DCN_UNIVERSAL,
	69	+};
	70	+
	71	+struct dc_plane_cap {
	72	+ enum dc_plane_type type;
	73	+ uint32_t blends_with_above : 1;
	74	+ uint32_t blends_with_below : 1;
	75	+ uint32_t per_pixel_alpha : 1;
	76	+ struct {
	77	+ uint32_t argb8888 : 1;
	78	+ uint32_t nv12 : 1;
	79	+ uint32_t fp16 : 1;
	80	+ uint32_t p010 : 1;
	81	+ uint32_t ayuv : 1;
	82	+ } pixel_format_support;
	83	+ // max upscaling factor x1000
	84	+ // upscaling factors are always >= 1
	85	+ // for example, 1080p -> 8K is 4.0, or 4000 raw value
	86	+ struct {
	87	+ uint32_t argb8888;
	88	+ uint32_t nv12;
	89	+ uint32_t fp16;
	90	+ } max_upscale_factor;
	91	+ // max downscale factor x1000
	92	+ // downscale factors are always <= 1
	93	+ // for example, 8K -> 1080p is 0.25, or 250 raw value
	94	+ struct {
	95	+ uint32_t argb8888;
	96	+ uint32_t nv12;
	97	+ uint32_t fp16;
	98	+ } max_downscale_factor;
	99	+ // minimal width/height
	100	+ uint32_t min_width;
	101	+ uint32_t min_height;
	102	+};
	103	+
	104	+// Color management caps (DPP and MPC)
	105	+struct rom_curve_caps {
	106	+ uint16_t srgb : 1;
	107	+ uint16_t bt2020 : 1;
	108	+ uint16_t gamma2_2 : 1;
	109	+ uint16_t pq : 1;
	110	+ uint16_t hlg : 1;
	111	+};
	112	+
	113	+struct dpp_color_caps {
	114	+ uint16_t dcn_arch : 1; // all DCE generations treated the same
	115	+ // input lut is different than most LUTs, just plain 256-entry lookup
	116	+ uint16_t input_lut_shared : 1; // shared with DGAM
	117	+ uint16_t icsc : 1;
	118	+ uint16_t dgam_ram : 1;
	119	+ uint16_t post_csc : 1; // before gamut remap
	120	+ uint16_t gamma_corr : 1;
	121	+
	122	+ // hdr_mult and gamut remap always available in DPP (in that order)
	123	+ // 3d lut implies shaper LUT,
	124	+ // it may be shared with MPC - check MPC:shared_3d_lut flag
	125	+ uint16_t hw_3d_lut : 1;
	126	+ uint16_t ogam_ram : 1; // blnd gam
	127	+ uint16_t ocsc : 1;
	128	+ struct rom_curve_caps dgam_rom_caps;
	129	+ struct rom_curve_caps ogam_rom_caps;
	130	+};
	131	+
	132	+struct mpc_color_caps {
	133	+ uint16_t gamut_remap : 1;
	134	+ uint16_t ogam_ram : 1;
	135	+ uint16_t ocsc : 1;
	136	+ uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
	137	+ uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
	138	+
	139	+ struct rom_curve_caps ogam_rom_caps;
	140	+};
	141	+
	142	+struct dc_color_caps {
	143	+ struct dpp_color_caps dpp;
	144	+ struct mpc_color_caps mpc;
61	145	};
62	146
63	147	struct dc_caps {
..	..	@@ -80,6 +164,18 @@
80	164	bool force_dp_tps4_for_cp2520;
81	165	bool disable_dp_clk_share;
82	166	bool psp_setup_panel_mode;
	167	+ bool extended_aux_timeout_support;
	168	+ bool dmcub_support;
	169	+ enum dp_protocol_version max_dp_protocol_version;
	170	+ struct dc_plane_cap planes[MAX_PLANES];
	171	+ struct dc_color_caps color;
	172	+};
	173	+
	174	+struct dc_bug_wa {
	175	+ bool no_connect_phy_config;
	176	+ bool dedcn20_305_wa;
	177	+ bool skip_clock_update;
	178	+ bool lt_early_cr_pattern;
83	179	};
84	180
85	181	struct dc_dcc_surface_param {
..	..	@@ -93,6 +189,15 @@
93	189	unsigned int max_compressed_blk_size;
94	190	unsigned int max_uncompressed_blk_size;
95	191	bool independent_64b_blks;
	192	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	193	+ //These bitfields to be used starting with DCN 3.0
	194	+ struct {
	195	+ uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
	196	+ uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0
	197	+ uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0
	198	+ uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)
	199	+ } dcc_controls;
	200	+#endif
96	201	};
97	202
98	203	struct dc_surface_dcc_cap {
..	..	@@ -111,11 +216,14 @@
111	216	bool const_color_support;
112	217	};
113	218
114		-struct dc_static_screen_events {
115		- bool force_trigger;
116		- bool cursor_update;
117		- bool surface_update;
118		- bool overlay_update;
	219	+struct dc_static_screen_params {
	220	+ struct {
	221	+ bool force_trigger;
	222	+ bool cursor_update;
	223	+ bool surface_update;
	224	+ bool overlay_update;
	225	+ } triggers;
	226	+ unsigned int num_frames;
119	227	};
120	228
121	229
..	..	@@ -170,12 +278,29 @@
170	278	struct dc_config {
171	279	bool gpu_vm_support;
172	280	bool disable_disp_pll_sharing;
	281	+ bool fbc_support;
	282	+ bool optimize_edp_link_rate;
	283	+ bool disable_fractional_pwm;
	284	+ bool allow_seamless_boot_optimization;
	285	+ bool power_down_display_on_boot;
	286	+ bool edp_not_connected;
	287	+ bool force_enum_edp;
	288	+ bool forced_clocks;
	289	+ bool allow_lttpr_non_transparent_mode;
	290	+ bool multi_mon_pp_mclk_switch;
	291	+ bool disable_dmcu;
	292	+ bool enable_4to1MPC;
	293	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	294	+ bool clamp_min_dcfclk;
	295	+#endif
173	296	};
174	297
175	298	enum visual_confirm {
176	299	VISUAL_CONFIRM_DISABLE = 0,
177	300	VISUAL_CONFIRM_SURFACE = 1,
178	301	VISUAL_CONFIRM_HDR = 2,
	302	+ VISUAL_CONFIRM_MPCTREE = 4,
	303	+ VISUAL_CONFIRM_PSR = 5,
179	304	};
180	305
181	306	enum dcc_option {
..	..	@@ -194,6 +319,19 @@
194	319	WM_REPORT_DEFAULT = 0,
195	320	WM_REPORT_OVERRIDE = 1,
196	321	};
	322	+enum dtm_pstate{
	323	+ dtm_level_p0 = 0,/highest voltage/
	324	+ dtm_level_p1,
	325	+ dtm_level_p2,
	326	+ dtm_level_p3,
	327	+ dtm_level_p4,/when active_display_count = 0/
	328	+};
	329	+
	330	+enum dcn_pwr_state {
	331	+ DCN_PWR_STATE_UNKNOWN = -1,
	332	+ DCN_PWR_STATE_MISSION_MODE = 0,
	333	+ DCN_PWR_STATE_LOW_POWER = 3,
	334	+};
197	335
198	336	/*
199	337	* For any clocks that may differ per pipe
..	..	@@ -201,14 +339,78 @@
201	339	*/
202	340	struct dc_clocks {
203	341	int dispclk_khz;
204		- int max_supported_dppclk_khz;
205	342	int dppclk_khz;
	343	+ int disp_dpp_voltage_level_khz;
206	344	int dcfclk_khz;
207	345	int socclk_khz;
208	346	int dcfclk_deep_sleep_khz;
209	347	int fclk_khz;
210	348	int phyclk_khz;
	349	+ int dramclk_khz;
	350	+ bool p_state_change_support;
	351	+ enum dcn_pwr_state pwr_state;
	352	+ /*
	353	+ * Elements below are not compared for the purposes of
	354	+ * optimization required
	355	+ */
	356	+ bool prev_p_state_change_support;
	357	+ enum dtm_pstate dtm_level;
	358	+ int max_supported_dppclk_khz;
	359	+ int max_supported_dispclk_khz;
	360	+ int bw_dppclk_khz; /a copy of dppclk_khz/
	361	+ int bw_dispclk_khz;
211	362	};
	363	+
	364	+struct dc_bw_validation_profile {
	365	+ bool enable;
	366	+
	367	+ unsigned long long total_ticks;
	368	+ unsigned long long voltage_level_ticks;
	369	+ unsigned long long watermark_ticks;
	370	+ unsigned long long rq_dlg_ticks;
	371	+
	372	+ unsigned long long total_count;
	373	+ unsigned long long skip_fast_count;
	374	+ unsigned long long skip_pass_count;
	375	+ unsigned long long skip_fail_count;
	376	+};
	377	+
	378	+#define BW_VAL_TRACE_SETUP() \
	379	+ unsigned long long end_tick = 0; \
	380	+ unsigned long long voltage_level_tick = 0; \
	381	+ unsigned long long watermark_tick = 0; \
	382	+ unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
	383	+ dm_get_timestamp(dc->ctx) : 0
	384	+
	385	+#define BW_VAL_TRACE_COUNT() \
	386	+ if (dc->debug.bw_val_profile.enable) \
	387	+ dc->debug.bw_val_profile.total_count++
	388	+
	389	+#define BW_VAL_TRACE_SKIP(status) \
	390	+ if (dc->debug.bw_val_profile.enable) { \
	391	+ if (!voltage_level_tick) \
	392	+ voltage_level_tick = dm_get_timestamp(dc->ctx); \
	393	+ dc->debug.bw_val_profile.skip_ ## status ## _count++; \
	394	+ }
	395	+
	396	+#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
	397	+ if (dc->debug.bw_val_profile.enable) \
	398	+ voltage_level_tick = dm_get_timestamp(dc->ctx)
	399	+
	400	+#define BW_VAL_TRACE_END_WATERMARKS() \
	401	+ if (dc->debug.bw_val_profile.enable) \
	402	+ watermark_tick = dm_get_timestamp(dc->ctx)
	403	+
	404	+#define BW_VAL_TRACE_FINISH() \
	405	+ if (dc->debug.bw_val_profile.enable) { \
	406	+ end_tick = dm_get_timestamp(dc->ctx); \
	407	+ dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
	408	+ dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
	409	+ if (watermark_tick) { \
	410	+ dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
	411	+ dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
	412	+ } \
	413	+ }
212	414
213	415	struct dc_debug_options {
214	416	enum visual_confirm visual_confirm;
..	..	@@ -232,25 +434,30 @@
232	434	bool disable_dfs_bypass;
233	435	bool disable_dpp_power_gate;
234	436	bool disable_hubp_power_gate;
	437	+ bool disable_dsc_power_gate;
	438	+ int dsc_min_slice_height_override;
	439	+ int dsc_bpp_increment_div;
	440	+ bool native422_support;
235	441	bool disable_pplib_wm_range;
236	442	enum wm_report_mode pplib_wm_report_mode;
237	443	unsigned int min_disp_clk_khz;
	444	+ unsigned int min_dpp_clk_khz;
238	445	int sr_exit_time_dpm0_ns;
239	446	int sr_enter_plus_exit_time_dpm0_ns;
240	447	int sr_exit_time_ns;
241	448	int sr_enter_plus_exit_time_ns;
242	449	int urgent_latency_ns;
	450	+ uint32_t underflow_assert_delay_us;
243	451	int percent_of_ideal_drambw;
244	452	int dram_clock_change_latency_ns;
245	453	bool optimized_watermark;
246	454	int always_scale;
247	455	bool disable_pplib_clock_request;
248	456	bool disable_clock_gate;
	457	+ bool disable_mem_low_power;
249	458	bool disable_dmcu;
250	459	bool disable_psr;
251	460	bool force_abm_enable;
252		- bool disable_hbup_pg;
253		- bool disable_dpp_pg;
254	461	bool disable_stereo_support;
255	462	bool vsr_support;
256	463	bool performance_trace;
..	..	@@ -262,6 +469,41 @@
262	469	bool scl_reset_length10;
263	470	bool hdmi20_disable;
264	471	bool skip_detection_link_training;
	472	+ bool edid_read_retry_times;
	473	+ bool remove_disconnect_edp;
	474	+ unsigned int force_odm_combine; //bit vector based on otg inst
	475	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	476	+ unsigned int force_odm_combine_4to1; //bit vector based on otg inst
	477	+#endif
	478	+ unsigned int force_fclk_khz;
	479	+ bool enable_tri_buf;
	480	+ bool dmub_offload_enabled;
	481	+ bool dmcub_emulation;
	482	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	483	+ bool disable_idle_power_optimizations;
	484	+#endif
	485	+ bool dmub_command_table; /* for testing only */
	486	+ struct dc_bw_validation_profile bw_val_profile;
	487	+ bool disable_fec;
	488	+ bool disable_48mhz_pwrdwn;
	489	+ /* This forces a hard min on the DCFCLK requested to SMU/PP
	490	+ * watermarks are not affected.
	491	+ */
	492	+ unsigned int force_min_dcfclk_mhz;
	493	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	494	+ int dwb_fi_phase;
	495	+#endif
	496	+ bool disable_timing_sync;
	497	+ bool cm_in_bypass;
	498	+ int force_clock_mode;/every mode change./
	499	+
	500	+ bool disable_dram_clock_change_vactive_support;
	501	+ bool validate_dml_output;
	502	+ bool enable_dmcub_surface_flip;
	503	+ bool usbc_combo_phy_reset_wa;
	504	+ bool disable_dsc;
	505	+ bool enable_dram_clock_change_one_display_vactive;
	506	+ bool force_ignore_link_settings;
265	507	};
266	508
267	509	struct dc_debug_data {
..	..	@@ -270,17 +512,65 @@
270	512	uint32_t auxErrorCount;
271	513	};
272	514
	515	+struct dc_phy_addr_space_config {
	516	+ struct {
	517	+ uint64_t start_addr;
	518	+ uint64_t end_addr;
	519	+ uint64_t fb_top;
	520	+ uint64_t fb_offset;
	521	+ uint64_t fb_base;
	522	+ uint64_t agp_top;
	523	+ uint64_t agp_bot;
	524	+ uint64_t agp_base;
	525	+ } system_aperture;
	526	+
	527	+ struct {
	528	+ uint64_t page_table_start_addr;
	529	+ uint64_t page_table_end_addr;
	530	+ uint64_t page_table_base_addr;
	531	+ } gart_config;
	532	+
	533	+ bool valid;
	534	+ bool is_hvm_enabled;
	535	+ uint64_t page_table_default_page_addr;
	536	+};
	537	+
	538	+struct dc_virtual_addr_space_config {
	539	+ uint64_t page_table_base_addr;
	540	+ uint64_t page_table_start_addr;
	541	+ uint64_t page_table_end_addr;
	542	+ uint32_t page_table_block_size_in_bytes;
	543	+ uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
	544	+};
	545	+
	546	+struct dc_bounding_box_overrides {
	547	+ int sr_exit_time_ns;
	548	+ int sr_enter_plus_exit_time_ns;
	549	+ int urgent_latency_ns;
	550	+ int percent_of_ideal_drambw;
	551	+ int dram_clock_change_latency_ns;
	552	+ int dummy_clock_change_latency_ns;
	553	+ /* This forces a hard min on the DCFCLK we use
	554	+ * for DML. Unlike the debug option for forcing
	555	+ * DCFCLK, this override affects watermark calculations
	556	+ */
	557	+ int min_dcfclk_mhz;
	558	+};
273	559
274	560	struct dc_state;
275	561	struct resource_pool;
276	562	struct dce_hwseq;
	563	+struct gpu_info_soc_bounding_box_v1_0;
277	564	struct dc {
278	565	struct dc_versions versions;
279	566	struct dc_caps caps;
280	567	struct dc_cap_funcs cap_funcs;
281	568	struct dc_config config;
282	569	struct dc_debug_options debug;
	570	+ struct dc_bounding_box_overrides bb_overrides;
	571	+ struct dc_bug_wa work_arounds;
283	572	struct dc_context *ctx;
	573	+ struct dc_phy_addr_space_config vm_pa_config;
284	574
285	575	uint8_t link_count;
286	576	struct dc_link links[MAX_PIPES 2];
..	..	@@ -288,13 +578,15 @@
288	578	struct dc_state *current_state;
289	579	struct resource_pool *res_pool;
290	580
	581	+ struct clk_mgr *clk_mgr;
	582	+
291	583	/* Display Engine Clock levels */
292	584	struct dm_pp_clock_levels sclk_lvls;
293	585
294	586	/* Inputs into BW and WM calculations. */
295	587	struct bw_calcs_dceip *bw_dceip;
296	588	struct bw_calcs_vbios *bw_vbios;
297		-#ifdef CONFIG_DRM_AMD_DC_DCN1_0
	589	+#ifdef CONFIG_DRM_AMD_DC_DCN
298	590	struct dcn_soc_bounding_box *dcn_soc;
299	591	struct dcn_ip_params *dcn_ip;
300	592	struct display_mode_lib dml;
..	..	@@ -304,19 +596,25 @@
304	596	struct hw_sequencer_funcs hwss;
305	597	struct dce_hwseq *hwseq;
306	598
307		- /* temp store of dm_pp_display_configuration
308		- * to compare to see if display config changed
309		- */
310		- struct dm_pp_display_configuration prev_display_config;
311		-
	599	+ /* Require to optimize clocks and bandwidth for added/removed planes */
312	600	bool optimized_required;
	601	+ bool wm_optimized_required;
	602	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	603	+ bool idle_optimizations_allowed;
	604	+#endif
313	605
314		- bool apply_edp_fast_boot_optimization;
	606	+ /* Require to maintain clocks and bandwidth for UEFI enabled HW */
	607	+ int optimize_seamless_boot_streams;
315	608
316	609	/* FBC compressor */
317	610	struct compressor *fbc_compressor;
318	611
319	612	struct dc_debug_data debug_data;
	613	+ struct dpcd_vendor_signature vendor_signature;
	614	+
	615	+ const char *build_id;
	616	+ struct vm_helper *vm_helper;
	617	+ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
320	618	};
321	619
322	620	enum frame_buffer_mode {
..	..	@@ -338,6 +636,7 @@
338	636	struct hw_asic_id asic_id;
339	637	void driver; / ctx */
340	638	struct cgs_device *cgs_device;
	639	+ struct dc_bounding_box_overrides bb_overrides;
341	640
342	641	int num_virtual_links;
343	642	/*
..	..	@@ -347,12 +646,42 @@
347	646	struct dc_bios *vbios_override;
348	647	enum dce_environment dce_environment;
349	648
	649	+ struct dmub_offload_funcs *dmub_if;
	650	+ struct dc_reg_helper_state *dmub_offload;
	651	+
350	652	struct dc_config flags;
351		- uint32_t log_mask;
	653	+ uint64_t log_mask;
	654	+
	655	+ /**
	656	+ * gpu_info FW provided soc bounding box struct or 0 if not
	657	+ * available in FW
	658	+ */
	659	+ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
	660	+ struct dpcd_vendor_signature vendor_signature;
	661	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	662	+ bool force_smu_not_present;
	663	+#endif
	664	+ bool force_ignore_link_settings;
	665	+};
	666	+
	667	+struct dc_callback_init {
	668	+#ifdef CONFIG_DRM_AMD_DC_HDCP
	669	+ struct cp_psp cp_psp;
	670	+#else
	671	+ uint8_t reserved;
	672	+#endif
352	673	};
353	674
354	675	struct dc dc_create(const struct dc_init_data init_params);
	676	+void dc_hardware_init(struct dc *dc);
355	677
	678	+int dc_get_vmid_use_vector(struct dc *dc);
	679	+void dc_setup_vm_context(struct dc dc, struct dc_virtual_addr_space_config va_config, int vmid);
	680	+/* Returns the number of vmids supported */
	681	+int dc_setup_system_context(struct dc dc, struct dc_phy_addr_space_config pa_config);
	682	+void dc_init_callbacks(struct dc *dc,
	683	+ const struct dc_callback_init *init_params);
	684	+void dc_deinit_callbacks(struct dc *dc);
356	685	void dc_destroy(struct dc **dc);
357	686
358	687	/*******************************************************************************
..	..	@@ -406,8 +735,11 @@
406	735	TRANSFER_FUNCTION_UNITY,
407	736	TRANSFER_FUNCTION_HLG,
408	737	TRANSFER_FUNCTION_HLG12,
409		- TRANSFER_FUNCTION_GAMMA22
	738	+ TRANSFER_FUNCTION_GAMMA22,
	739	+ TRANSFER_FUNCTION_GAMMA24,
	740	+ TRANSFER_FUNCTION_GAMMA26
410	741	};
	742	+
411	743
412	744	struct dc_transfer_func {
413	745	struct kref refcount;
..	..	@@ -415,13 +747,33 @@
415	747	enum dc_transfer_func_predefined tf;
416	748	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
417	749	uint32_t sdr_ref_white_level;
418		- struct dc_context *ctx;
419	750	union {
420	751	struct pwl_params pwl;
421	752	struct dc_transfer_func_distributed_points tf_pts;
422	753	};
423	754	};
424	755
	756	+
	757	+union dc_3dlut_state {
	758	+ struct {
	759	+ uint32_t initialized:1; /if 3dlut is went through color module for initialization /
	760	+ uint32_t rmu_idx_valid:1; /if mux settings are valid/
	761	+ uint32_t rmu_mux_num:3; /index of mux to use/
	762	+ uint32_t mpc_rmu0_mux:4; /select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3/
	763	+ uint32_t mpc_rmu1_mux:4;
	764	+ uint32_t mpc_rmu2_mux:4;
	765	+ uint32_t reserved:15;
	766	+ } bits;
	767	+ uint32_t raw;
	768	+};
	769	+
	770	+
	771	+struct dc_3dlut {
	772	+ struct kref refcount;
	773	+ struct tetrahedral_params lut_3d;
	774	+ struct fixed31_32 hdr_multiplier;
	775	+ union dc_3dlut_state state;
	776	+};
425	777	/*
426	778	* This structure is filled in by dc_surface_get_status and contains
427	779	* the last requested address and the currently active address so the called
..	..	@@ -437,11 +789,14 @@
437	789	union surface_update_flags {
438	790
439	791	struct {
	792	+ uint32_t addr_update:1;
440	793	/* Medium updates */
441	794	uint32_t dcc_change:1;
442	795	uint32_t color_space_change:1;
443	796	uint32_t horizontal_mirror_change:1;
444	797	uint32_t per_pixel_alpha_change:1;
	798	+ uint32_t global_alpha_change:1;
	799	+ uint32_t hdr_mult:1;
445	800	uint32_t rotation_change:1;
446	801	uint32_t swizzle_change:1;
447	802	uint32_t scaling_change:1;
..	..	@@ -451,6 +806,8 @@
451	806	uint32_t coeff_reduction_change:1;
452	807	uint32_t output_tf_change:1;
453	808	uint32_t pixel_format_change:1;
	809	+ uint32_t plane_size_change:1;
	810	+ uint32_t gamut_remap_change:1;
454	811
455	812	/* Full updates */
456	813	uint32_t new_plane:1;
..	..	@@ -468,12 +825,13 @@
468	825	struct dc_plane_state {
469	826	struct dc_plane_address address;
470	827	struct dc_plane_flip_time time;
	828	+ bool triplebuffer_flips;
471	829	struct scaling_taps scaling_quality;
472	830	struct rect src_rect;
473	831	struct rect dst_rect;
474	832	struct rect clip_rect;
475	833
476		- union plane_size plane_size;
	834	+ struct plane_size plane_size;
477	835	union dc_tiling_info tiling_info;
478	836
479	837	struct dc_plane_dcc_param dcc;
..	..	@@ -483,22 +841,33 @@
483	841	struct dc_bias_and_scale *bias_and_scale;
484	842	struct dc_csc_transform input_csc_color_matrix;
485	843	struct fixed31_32 coeff_reduction_factor;
486		- uint32_t sdr_white_level;
	844	+ struct fixed31_32 hdr_mult;
	845	+ struct colorspace_transform gamut_remap_matrix;
487	846
488	847	// TODO: No longer used, remove
489	848	struct dc_hdr_static_metadata hdr_static_ctx;
490	849
491	850	enum dc_color_space color_space;
492	851
	852	+ struct dc_3dlut *lut3d_func;
	853	+ struct dc_transfer_func *in_shaper_func;
	854	+ struct dc_transfer_func *blend_tf;
	855	+
	856	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	857	+ struct dc_transfer_func *gamcor_tf;
	858	+#endif
493	859	enum surface_pixel_format format;
494	860	enum dc_rotation_angle rotation;
495	861	enum plane_stereo_format stereo_format;
496	862
497	863	bool is_tiling_rotated;
498	864	bool per_pixel_alpha;
	865	+ bool global_alpha;
	866	+ int global_alpha_value;
499	867	bool visible;
500	868	bool flip_immediate;
501	869	bool horizontal_mirror;
	870	+ int layer_index;
502	871
503	872	union surface_update_flags update_flags;
504	873	/* private to DC core */
..	..	@@ -514,18 +883,20 @@
514	883	};
515	884
516	885	struct dc_plane_info {
517		- union plane_size plane_size;
	886	+ struct plane_size plane_size;
518	887	union dc_tiling_info tiling_info;
519	888	struct dc_plane_dcc_param dcc;
520	889	enum surface_pixel_format format;
521	890	enum dc_rotation_angle rotation;
522	891	enum plane_stereo_format stereo_format;
523	892	enum dc_color_space color_space;
524		- unsigned int sdr_white_level;
525	893	bool horizontal_mirror;
526	894	bool visible;
527	895	bool per_pixel_alpha;
	896	+ bool global_alpha;
	897	+ int global_alpha_value;
528	898	bool input_csc_enabled;
	899	+ int layer_index;
529	900	};
530	901
531	902	struct dc_scaling_info {
..	..	@@ -542,7 +913,7 @@
542	913	const struct dc_flip_addrs *flip_addr;
543	914	const struct dc_plane_info *plane_info;
544	915	const struct dc_scaling_info *scaling_info;
545		-
	916	+ struct fixed31_32 hdr_mult;
546	917	/* following updates require alloc/sleep/spin that is not isr safe,
547	918	* null means no updates
548	919	*/
..	..	@@ -551,6 +922,10 @@
551	922
552	923	const struct dc_csc_transform *input_csc_color_matrix;
553	924	const struct fixed31_32 *coeff_reduction_factor;
	925	+ const struct dc_transfer_func *func_shaper;
	926	+ const struct dc_3dlut *lut3d_func;
	927	+ const struct dc_transfer_func *blend_tf;
	928	+ const struct colorspace_transform *gamut_remap_matrix;
554	929	};
555	930
556	931	/*
..	..	@@ -571,6 +946,9 @@
571	946	void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
572	947	struct dc_transfer_func *dc_create_transfer_func(void);
573	948
	949	+struct dc_3dlut *dc_create_3dlut_func(void);
	950	+void dc_3dlut_func_release(struct dc_3dlut *lut);
	951	+void dc_3dlut_func_retain(struct dc_3dlut *lut);
574	952	/*
575	953	* This structure holds a surface address. There could be multiple addresses
576	954	* in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
..	..	@@ -581,6 +959,7 @@
581	959	unsigned int flip_timestamp_in_us;
582	960	bool flip_immediate;
583	961	/* TODO: add flip duration for FreeSync */
	962	+ bool triplebuffer_flips;
584	963	};
585	964
586	965	bool dc_post_update_surfaces_to_stream(
..	..	@@ -597,16 +976,38 @@
597	976	uint8_t plane_count;
598	977	};
599	978
	979	+bool dc_validate_seamless_boot_timing(const struct dc *dc,
	980	+ const struct dc_sink *sink,
	981	+ struct dc_crtc_timing *crtc_timing);
	982	+
600	983	enum dc_status dc_validate_plane(struct dc dc, const struct dc_plane_state plane_state);
601	984
	985	+void get_clock_requirements_for_state(struct dc_state state, struct AsicStateEx info);
	986	+
	987	+bool dc_set_generic_gpio_for_stereo(bool enable,
	988	+ struct gpio_service *gpio_service);
	989	+
	990	+/*
	991	+ * fast_validate: we return after determining if we can support the new state,
	992	+ * but before we populate the programming info
	993	+ */
602	994	enum dc_status dc_validate_global_state(
603	995	struct dc *dc,
604		- struct dc_state *new_ctx);
	996	+ struct dc_state *new_ctx,
	997	+ bool fast_validate);
605	998
606	999
607	1000	void dc_resource_state_construct(
608	1001	const struct dc *dc,
609	1002	struct dc_state *dst_ctx);
	1003	+
	1004	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	1005	+bool dc_acquire_release_mpc_3dlut(
	1006	+ struct dc *dc, bool acquire,
	1007	+ struct dc_stream_state *stream,
	1008	+ struct dc_3dlut **lut,
	1009	+ struct dc_transfer_func **shaper);
	1010	+#endif
610	1011
611	1012	void dc_resource_state_copy_construct(
612	1013	const struct dc_state *src_ctx,
..	..	@@ -617,6 +1018,8 @@
617	1018	struct dc_state *dst_ctx);
618	1019
619	1020	void dc_resource_state_destruct(struct dc_state *context);
	1021	+
	1022	+bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
620	1023
621	1024	/*
622	1025	* TODO update to make it about validation sets
..	..	@@ -629,8 +1032,10 @@
629	1032	*/
630	1033	bool dc_commit_state(struct dc dc, struct dc_state context);
631	1034
	1035	+void dc_power_down_on_boot(struct dc *dc);
632	1036
633		-struct dc_state *dc_create_state(void);
	1037	+struct dc_state dc_create_state(struct dc dc);
	1038	+struct dc_state dc_copy_state(struct dc_state src_ctx);
634	1039	void dc_retain_state(struct dc_state *context);
635	1040	void dc_release_state(struct dc_state *context);
636	1041
..	..	@@ -642,9 +1047,16 @@
642	1047	union dpcd_rev dpcd_rev;
643	1048	union max_lane_count max_ln_count;
644	1049	union max_down_spread max_down_spread;
	1050	+ union dprx_feature dprx_feature;
	1051	+
	1052	+ /* valid only for eDP v1.4 or higher*/
	1053	+ uint8_t edp_supported_link_rates_count;
	1054	+ enum dc_link_rate edp_supported_link_rates[8];
645	1055
646	1056	/* dongle type (DP converter, CV smart dongle) */
647	1057	enum display_dongle_type dongle_type;
	1058	+ /* branch device or sink device */
	1059	+ bool is_branch_dev;
648	1060	/* Dongle's downstream count. */
649	1061	union sink_count sink_count;
650	1062	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
..	..	@@ -664,10 +1076,63 @@
664	1076	bool allow_invalid_MSA_timing_param;
665	1077	bool panel_mode_edp;
666	1078	bool dpcd_display_control_capable;
	1079	+ bool ext_receiver_cap_field_present;
	1080	+ union dpcd_fec_capability fec_cap;
	1081	+ struct dpcd_dsc_capabilities dsc_caps;
	1082	+ struct dc_lttpr_caps lttpr_caps;
	1083	+ struct psr_caps psr_caps;
	1084	+
667	1085	};
	1086	+
	1087	+union dpcd_sink_ext_caps {
	1088	+ struct {
	1089	+ /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
	1090	+ * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
	1091	+ */
	1092	+ uint8_t sdr_aux_backlight_control : 1;
	1093	+ uint8_t hdr_aux_backlight_control : 1;
	1094	+ uint8_t reserved_1 : 2;
	1095	+ uint8_t oled : 1;
	1096	+ uint8_t reserved : 3;
	1097	+ } bits;
	1098	+ uint8_t raw;
	1099	+};
	1100	+
	1101	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	1102	+union hdcp_rx_caps {
	1103	+ struct {
	1104	+ uint8_t version;
	1105	+ uint8_t reserved;
	1106	+ struct {
	1107	+ uint8_t repeater : 1;
	1108	+ uint8_t hdcp_capable : 1;
	1109	+ uint8_t reserved : 6;
	1110	+ } byte0;
	1111	+ } fields;
	1112	+ uint8_t raw[3];
	1113	+};
	1114	+
	1115	+union hdcp_bcaps {
	1116	+ struct {
	1117	+ uint8_t HDCP_CAPABLE:1;
	1118	+ uint8_t REPEATER:1;
	1119	+ uint8_t RESERVED:6;
	1120	+ } bits;
	1121	+ uint8_t raw;
	1122	+};
	1123	+
	1124	+struct hdcp_caps {
	1125	+ union hdcp_rx_caps rx_caps;
	1126	+ union hdcp_bcaps bcaps;
	1127	+};
	1128	+#endif
668	1129
669	1130	#include "dc_link.h"
670	1131
	1132	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	1133	+uint32_t dc_get_opp_for_plane(struct dc dc, struct dc_plane_state plane);
	1134	+
	1135	+#endif
671	1136	/*******************************************************************************
672	1137	* Sink Interfaces - A sink corresponds to a display output device
673	1138	******************************************************************************/
..	..	@@ -684,6 +1149,17 @@
684	1149	};
685	1150
686	1151
	1152	+struct dc_sink_dsc_caps {
	1153	+ // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
	1154	+ // 'false' if they are sink's DSC caps
	1155	+ bool is_virtual_dpcd_dsc;
	1156	+ struct dsc_dec_dpcd_caps dsc_dec_caps;
	1157	+};
	1158	+
	1159	+struct dc_sink_fec_caps {
	1160	+ bool is_rx_fec_supported;
	1161	+ bool is_topology_fec_supported;
	1162	+};
687	1163
688	1164	/*
689	1165	* The sink structure contains EDID and other display device properties
..	..	@@ -697,6 +1173,11 @@
697	1173	void *priv;
698	1174	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
699	1175	bool converter_disable_audio;
	1176	+ bool is_mst_legacy;
	1177	+ struct dc_sink_dsc_caps dsc_caps;
	1178	+ struct dc_sink_fec_caps fec_caps;
	1179	+
	1180	+ bool is_vsc_sdp_colorimetry_supported;
700	1181
701	1182	/* private to DC core */
702	1183	struct dc_link *link;
..	..	@@ -719,6 +1200,7 @@
719	1200	struct dc_link *link;
720	1201	uint32_t dongle_max_pix_clk;
721	1202	bool converter_disable_audio;
	1203	+ bool sink_is_legacy;
722	1204	};
723	1205
724	1206	struct dc_sink dc_sink_create(const struct dc_sink_init_data init_params);
..	..	@@ -751,4 +1233,46 @@
751	1233	enum dc_acpi_cm_power_state power_state);
752	1234	void dc_resume(struct dc *dc);
753	1235
	1236	+void dc_power_down_on_boot(struct dc *dc);
	1237	+
	1238	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	1239	+/*
	1240	+ * HDCP Interfaces
	1241	+ */
	1242	+enum hdcp_message_status dc_process_hdcp_msg(
	1243	+ enum signal_type signal,
	1244	+ struct dc_link *link,
	1245	+ struct hdcp_protection_message *message_info);
	1246	+#endif
	1247	+bool dc_is_dmcu_initialized(struct dc *dc);
	1248	+
	1249	+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
	1250	+void dc_get_clock(struct dc dc, enum dc_clock_type clock_type, struct dc_clock_config clock_cfg);
	1251	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	1252	+
	1253	+bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
	1254	+ struct dc_plane_state *plane);
	1255	+
	1256	+void dc_allow_idle_optimizations(struct dc *dc, bool allow);
	1257	+
	1258	+/*
	1259	+ * blank all streams, and set min and max memory clock to
	1260	+ * lowest and highest DPM level, respectively
	1261	+ */
	1262	+void dc_unlock_memory_clock_frequency(struct dc *dc);
	1263	+
	1264	+/*
	1265	+ * set min memory clock to the min required for current mode,
	1266	+ * max to maxDPM, and unblank streams
	1267	+ */
	1268	+void dc_lock_memory_clock_frequency(struct dc *dc);
	1269	+
	1270	+#endif
	1271	+
	1272	+bool dc_set_psr_allow_active(struct dc *dc, bool enable);
	1273	+
	1274	+/*******************************************************************************
	1275	+ * DSC Interfaces
	1276	+ ******************************************************************************/
	1277	+#include "dc_dsc.h"
754	1278	#endif /* DC_INTERFACE_H_ */