~hc/RK356X_SDK_RELEASE.git

..	..	@@ -23,8 +23,10 @@
23	23	*
24	24	*/
25	25
	26	+#include <linux/slab.h>
	27	+
26	28	#include "dm_services.h"
27		-#include "atom.h"
	29	+#include "atomfirmware.h"
28	30	#include "dm_helpers.h"
29	31	#include "dc.h"
30	32	#include "grph_object_id.h"
..	..	@@ -42,45 +44,54 @@
42	44	#include "fixed31_32.h"
43	45	#include "dpcd_defs.h"
44	46	#include "dmcu.h"
45		-
46		-#include "dce/dce_11_0_d.h"
47		-#include "dce/dce_11_0_enum.h"
48		-#include "dce/dce_11_0_sh_mask.h"
	47	+#include "hw/clk_mgr.h"
	48	+#include "dce/dmub_psr.h"
	49	+#include "dmub/dmub_srv.h"
	50	+#include "inc/hw/panel_cntl.h"
49	51
50	52	#define DC_LOGGER_INIT(logger)
51		-
52	53
53	54	#define LINK_INFO(...) \
54	55	DC_LOG_HW_HOTPLUG( \
55	56	__VA_ARGS__)
56	57
	58	+#define RETIMER_REDRIVER_INFO(...) \
	59	+ DC_LOG_RETIMER_REDRIVER( \
	60	+ __VA_ARGS__)
57	61	/*******************************************************************************
58	62	* Private structures
59	63	******************************************************************************/
60	64
61	65	enum {
62		- LINK_RATE_REF_FREQ_IN_MHZ = 27,
63	66	PEAK_FACTOR_X1000 = 1006,
64	67	/*
65		- * Some receivers fail to train on first try and are good
66		- * on subsequent tries. 2 retries should be plenty. If we
67		- * don't have a successful training then we don't expect to
68		- * ever get one.
69		- */
	68	+ * Some receivers fail to train on first try and are good
	69	+ * on subsequent tries. 2 retries should be plenty. If we
	70	+ * don't have a successful training then we don't expect to
	71	+ * ever get one.
	72	+ */
70	73	LINK_TRAINING_MAX_VERIFY_RETRY = 2
71	74	};
72	75
73	76	/*******************************************************************************
74	77	* Private functions
75	78	******************************************************************************/
76		-static void destruct(struct dc_link *link)
	79	+static void dc_link_destruct(struct dc_link *link)
77	80	{
78	81	int i;
	82	+
	83	+ if (link->hpd_gpio) {
	84	+ dal_gpio_destroy_irq(&link->hpd_gpio);
	85	+ link->hpd_gpio = NULL;
	86	+ }
79	87
80	88	if (link->ddc)
81	89	dal_ddc_service_destroy(&link->ddc);
82	90
83		- if(link->link_enc)
	91	+ if (link->panel_cntl)
	92	+ link->panel_cntl->funcs->destroy(&link->panel_cntl);
	93	+
	94	+ if (link->link_enc)
84	95	link->link_enc->funcs->destroy(&link->link_enc);
85	96
86	97	if (link->local_sink)
..	..	@@ -91,8 +102,8 @@
91	102	}
92	103
93	104	struct gpio get_hpd_gpio(struct dc_bios dcb,
94		- struct graphics_object_id link_id,
95		- struct gpio_service *gpio_service)
	105	+ struct graphics_object_id link_id,
	106	+ struct gpio_service *gpio_service)
96	107	{
97	108	enum bp_result bp_result;
98	109	struct graphics_object_hpd_info hpd_info;
..	..	@@ -109,10 +120,9 @@
109	120	return NULL;
110	121	}
111	122
112		- return dal_gpio_service_create_irq(
113		- gpio_service,
114		- pin_info.offset,
115		- pin_info.mask);
	123	+ return dal_gpio_service_create_irq(gpio_service,
	124	+ pin_info.offset,
	125	+ pin_info.mask);
116	126	}
117	127
118	128	/*
..	..	@@ -127,13 +137,10 @@
127	137	* @return
128	138	* true on success, false otherwise
129	139	*/
130		-static bool program_hpd_filter(
131		- const struct dc_link *link)
	140	+static bool program_hpd_filter(const struct dc_link *link)
132	141	{
133	142	bool result = false;
134		-
135	143	struct gpio *hpd;
136		-
137	144	int delay_on_connect_in_ms = 0;
138	145	int delay_on_disconnect_in_ms = 0;
139	146
..	..	@@ -152,10 +159,10 @@
152	159	case SIGNAL_TYPE_DISPLAY_PORT_MST:
153	160	/* Program hpd filter to allow DP signal to settle */
154	161	/* 500: not able to detect MST <-> SST switch as HPD is low for
155		- * only 100ms on DELL U2413
156		- * 0: some passive dongle still show aux mode instead of i2c
157		- * 20-50:not enough to hide bouncing HPD with passive dongle.
158		- * also see intermittent i2c read issues.
	162	+ * only 100ms on DELL U2413
	163	+ * 0: some passive dongle still show aux mode instead of i2c
	164	+ * 20-50: not enough to hide bouncing HPD with passive dongle.
	165	+ * also see intermittent i2c read issues.
159	166	*/
160	167	delay_on_connect_in_ms = 80;
161	168	delay_on_disconnect_in_ms = 0;
..	..	@@ -168,7 +175,8 @@
168	175	}
169	176
170	177	/* Obtain HPD handle */
171		- hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
	178	+ hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
	179	+ link->ctx->gpio_service);
172	180
173	181	if (!hpd)
174	182	return result;
..	..	@@ -195,14 +203,33 @@
195	203	return result;
196	204	}
197	205
	206	+/**
	207	+ * dc_link_detect_sink() - Determine if there is a sink connected
	208	+ *
	209	+ * @type: Returned connection type
	210	+ * Does not detect downstream devices, such as MST sinks
	211	+ * or display connected through active dongles
	212	+ */
198	213	bool dc_link_detect_sink(struct dc_link link, enum dc_connection_type type)
199	214	{
200	215	uint32_t is_hpd_high = 0;
201	216	struct gpio *hpd_pin;
202	217
	218	+ if (link->connector_signal == SIGNAL_TYPE_LVDS) {
	219	+ *type = dc_connection_single;
	220	+ return true;
	221	+ }
	222	+
	223	+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
	224	+ /in case it is not on/
	225	+ link->dc->hwss.edp_power_control(link, true);
	226	+ link->dc->hwss.edp_wait_for_hpd_ready(link, true);
	227	+ }
	228	+
203	229	/* todo: may need to lock gpio access */
204		- hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
205		- if (hpd_pin == NULL)
	230	+ hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
	231	+ link->ctx->gpio_service);
	232	+ if (!hpd_pin)
206	233	goto hpd_gpio_failure;
207	234
208	235	dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
..	..	@@ -223,8 +250,7 @@
223	250	return false;
224	251	}
225	252
226		-static enum ddc_transaction_type get_ddc_transaction_type(
227		- enum signal_type sink_signal)
	253	+static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
228	254	{
229	255	enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
230	256
..	..	@@ -245,7 +271,8 @@
245	271	case SIGNAL_TYPE_DISPLAY_PORT_MST:
246	272	/* MST does not use I2COverAux, but there is the
247	273	* SPECIAL use case for "immediate dwnstrm device
248		- * access" (EPR#370830). */
	274	+ * access" (EPR#370830).
	275	+ */
249	276	transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
250	277	break;
251	278
..	..	@@ -256,9 +283,8 @@
256	283	return transaction_type;
257	284	}
258	285
259		-static enum signal_type get_basic_signal_type(
260		- struct graphics_object_id encoder,
261		- struct graphics_object_id downstream)
	286	+static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
	287	+ struct graphics_object_id downstream)
262	288	{
263	289	if (downstream.type == OBJECT_TYPE_CONNECTOR) {
264	290	switch (downstream.id) {
..	..	@@ -316,9 +342,9 @@
316	342	return SIGNAL_TYPE_NONE;
317	343	}
318	344
319		-/*
320		- * @brief
321		- * Check whether there is a dongle on DP connector
	345	+/**
	346	+ * dc_link_is_dp_sink_present() - Check if there is a native DP
	347	+ * or passive DP-HDMI dongle connected
322	348	*/
323	349	bool dc_link_is_dp_sink_present(struct dc_link *link)
324	350	{
..	..	@@ -344,10 +370,11 @@
344	370	/* Open GPIO and set it to I2C mode */
345	371	/* Note: this GpioMode_Input will be converted
346	372	* to GpioConfigType_I2cAuxDualMode in GPIO component,
347		- * which indicates we need additional delay */
	373	+ * which indicates we need additional delay
	374	+ */
348	375
349		- if (GPIO_RESULT_OK != dal_ddc_open(
350		- ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
	376	+ if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
	377	+ GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
351	378	dal_ddc_close(ddc);
352	379
353	380	return present;
..	..	@@ -381,25 +408,25 @@
381	408	* @brief
382	409	* Detect output sink type
383	410	*/
384		-static enum signal_type link_detect_sink(
385		- struct dc_link *link,
386		- enum dc_detect_reason reason)
	411	+static enum signal_type link_detect_sink(struct dc_link *link,
	412	+ enum dc_detect_reason reason)
387	413	{
388		- enum signal_type result = get_basic_signal_type(
389		- link->link_enc->id, link->link_id);
	414	+ enum signal_type result = get_basic_signal_type(link->link_enc->id,
	415	+ link->link_id);
390	416
391	417	/* Internal digital encoder will detect only dongles
392		- * that require digital signal */
	418	+ * that require digital signal
	419	+ */
393	420
394	421	/* Detection mechanism is different
395	422	* for different native connectors.
396	423	* LVDS connector supports only LVDS signal;
397	424	* PCIE is a bus slot, the actual connector needs to be detected first;
398	425	* eDP connector supports only eDP signal;
399		- * HDMI should check straps for audio */
	426	+ * HDMI should check straps for audio
	427	+ */
400	428
401	429	/* PCIE detects the actual connector on add-on board */
402		-
403	430	if (link->link_id.id == CONNECTOR_ID_PCIE) {
404	431	/* ZAZTODO implement PCIE add-on card detection */
405	432	}
..	..	@@ -407,8 +434,10 @@
407	434	switch (link->link_id.id) {
408	435	case CONNECTOR_ID_HDMI_TYPE_A: {
409	436	/* check audio support:
410		- * if native HDMI is not supported, switch to DVI */
411		- struct audio_support *aud_support = &link->dc->res_pool->audio_support;
	437	+ * if native HDMI is not supported, switch to DVI
	438	+ */
	439	+ struct audio_support *aud_support =
	440	+ &link->dc->res_pool->audio_support;
412	441
413	442	if (!aud_support->hdmi_audio_native)
414	443	if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
..	..	@@ -436,16 +465,15 @@
436	465	return result;
437	466	}
438	467
439		-static enum signal_type decide_signal_from_strap_and_dongle_type(
440		- enum display_dongle_type dongle_type,
441		- struct audio_support *audio_support)
	468	+static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
	469	+ struct audio_support *audio_support)
442	470	{
443	471	enum signal_type signal = SIGNAL_TYPE_NONE;
444	472
445	473	switch (dongle_type) {
446	474	case DISPLAY_DONGLE_DP_HDMI_DONGLE:
447	475	if (audio_support->hdmi_audio_on_dongle)
448		- signal = SIGNAL_TYPE_HDMI_TYPE_A;
	476	+ signal = SIGNAL_TYPE_HDMI_TYPE_A;
449	477	else
450	478	signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
451	479	break;
..	..	@@ -466,16 +494,14 @@
466	494	return signal;
467	495	}
468	496
469		-static enum signal_type dp_passive_dongle_detection(
470		- struct ddc_service *ddc,
471		- struct display_sink_capability *sink_cap,
472		- struct audio_support *audio_support)
	497	+static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
	498	+ struct display_sink_capability *sink_cap,
	499	+ struct audio_support *audio_support)
473	500	{
474		- dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
475		- ddc, sink_cap);
476		- return decide_signal_from_strap_and_dongle_type(
477		- sink_cap->dongle_type,
478		- audio_support);
	501	+ dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
	502	+
	503	+ return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
	504	+ audio_support);
479	505	}
480	506
481	507	static void link_disconnect_sink(struct dc_link *link)
..	..	@@ -494,15 +520,170 @@
494	520	link->local_sink = prev_sink;
495	521	}
496	522
	523	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	524	+bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
	525	+{
	526	+ bool ret = false;
497	527
498		-static bool detect_dp(
499		- struct dc_link *link,
500		- struct display_sink_capability *sink_caps,
501		- bool *converter_disable_audio,
502		- struct audio_support *audio_support,
503		- enum dc_detect_reason reason)
	528	+ switch (signal) {
	529	+ case SIGNAL_TYPE_DISPLAY_PORT:
	530	+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
	531	+ ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
	532	+ break;
	533	+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
	534	+ case SIGNAL_TYPE_DVI_DUAL_LINK:
	535	+ case SIGNAL_TYPE_HDMI_TYPE_A:
	536	+ /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
	537	+ * we can poll for bksv but some displays have an issue with this. Since its so rare
	538	+ * for a display to not be 1.4 capable, this assumtion is ok
	539	+ */
	540	+ ret = true;
	541	+ break;
	542	+ default:
	543	+ break;
	544	+ }
	545	+ return ret;
	546	+}
	547	+
	548	+bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
	549	+{
	550	+ bool ret = false;
	551	+
	552	+ switch (signal) {
	553	+ case SIGNAL_TYPE_DISPLAY_PORT:
	554	+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
	555	+ ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
	556	+ link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
	557	+ (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
	558	+ break;
	559	+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
	560	+ case SIGNAL_TYPE_DVI_DUAL_LINK:
	561	+ case SIGNAL_TYPE_HDMI_TYPE_A:
	562	+ ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
	563	+ break;
	564	+ default:
	565	+ break;
	566	+ }
	567	+
	568	+ return ret;
	569	+}
	570	+
	571	+static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
	572	+{
	573	+ struct hdcp_protection_message msg22;
	574	+ struct hdcp_protection_message msg14;
	575	+
	576	+ memset(&msg22, 0, sizeof(struct hdcp_protection_message));
	577	+ memset(&msg14, 0, sizeof(struct hdcp_protection_message));
	578	+ memset(link->hdcp_caps.rx_caps.raw, 0,
	579	+ sizeof(link->hdcp_caps.rx_caps.raw));
	580	+
	581	+ if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
	582	+ link->ddc->transaction_type ==
	583	+ DDC_TRANSACTION_TYPE_I2C_OVER_AUX) \|\|
	584	+ link->connector_signal == SIGNAL_TYPE_EDP) {
	585	+ msg22.data = link->hdcp_caps.rx_caps.raw;
	586	+ msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
	587	+ msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
	588	+ } else {
	589	+ msg22.data = &link->hdcp_caps.rx_caps.fields.version;
	590	+ msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
	591	+ msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
	592	+ }
	593	+ msg22.version = HDCP_VERSION_22;
	594	+ msg22.link = HDCP_LINK_PRIMARY;
	595	+ msg22.max_retries = 5;
	596	+ dc_process_hdcp_msg(signal, link, &msg22);
	597	+
	598	+ if (signal == SIGNAL_TYPE_DISPLAY_PORT \|\| signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
	599	+ enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED;
	600	+
	601	+ msg14.data = &link->hdcp_caps.bcaps.raw;
	602	+ msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
	603	+ msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
	604	+ msg14.version = HDCP_VERSION_14;
	605	+ msg14.link = HDCP_LINK_PRIMARY;
	606	+ msg14.max_retries = 5;
	607	+
	608	+ status = dc_process_hdcp_msg(signal, link, &msg14);
	609	+ }
	610	+
	611	+}
	612	+#endif
	613	+
	614	+static void read_current_link_settings_on_detect(struct dc_link *link)
	615	+{
	616	+ union lane_count_set lane_count_set = { {0} };
	617	+ uint8_t link_bw_set;
	618	+ uint8_t link_rate_set;
	619	+ uint32_t read_dpcd_retry_cnt = 10;
	620	+ enum dc_status status = DC_ERROR_UNEXPECTED;
	621	+ int i;
	622	+ union max_down_spread max_down_spread = { {0} };
	623	+
	624	+ // Read DPCD 00101h to find out the number of lanes currently set
	625	+ for (i = 0; i < read_dpcd_retry_cnt; i++) {
	626	+ status = core_link_read_dpcd(link,
	627	+ DP_LANE_COUNT_SET,
	628	+ &lane_count_set.raw,
	629	+ sizeof(lane_count_set));
	630	+ /* First DPCD read after VDD ON can fail if the particular board
	631	+ * does not have HPD pin wired correctly. So if DPCD read fails,
	632	+ * which it should never happen, retry a few times. Target worst
	633	+ * case scenario of 80 ms.
	634	+ */
	635	+ if (status == DC_OK) {
	636	+ link->cur_link_settings.lane_count =
	637	+ lane_count_set.bits.LANE_COUNT_SET;
	638	+ break;
	639	+ }
	640	+
	641	+ msleep(8);
	642	+ }
	643	+
	644	+ // Read DPCD 00100h to find if standard link rates are set
	645	+ core_link_read_dpcd(link, DP_LINK_BW_SET,
	646	+ &link_bw_set, sizeof(link_bw_set));
	647	+
	648	+ if (link_bw_set == 0) {
	649	+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
	650	+ /* If standard link rates are not being used,
	651	+ * Read DPCD 00115h to find the edp link rate set used
	652	+ */
	653	+ core_link_read_dpcd(link, DP_LINK_RATE_SET,
	654	+ &link_rate_set, sizeof(link_rate_set));
	655	+
	656	+ // edp_supported_link_rates_count = 0 for DP
	657	+ if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
	658	+ link->cur_link_settings.link_rate =
	659	+ link->dpcd_caps.edp_supported_link_rates[link_rate_set];
	660	+ link->cur_link_settings.link_rate_set = link_rate_set;
	661	+ link->cur_link_settings.use_link_rate_set = true;
	662	+ }
	663	+ } else {
	664	+ // Link Rate not found. Seamless boot may not work.
	665	+ ASSERT(false);
	666	+ }
	667	+ } else {
	668	+ link->cur_link_settings.link_rate = link_bw_set;
	669	+ link->cur_link_settings.use_link_rate_set = false;
	670	+ }
	671	+ // Read DPCD 00003h to find the max down spread.
	672	+ core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
	673	+ &max_down_spread.raw, sizeof(max_down_spread));
	674	+ link->cur_link_settings.link_spread =
	675	+ max_down_spread.bits.MAX_DOWN_SPREAD ?
	676	+ LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
	677	+}
	678	+
	679	+static bool detect_dp(struct dc_link *link,
	680	+ struct display_sink_capability *sink_caps,
	681	+ bool *converter_disable_audio,
	682	+ struct audio_support *audio_support,
	683	+ enum dc_detect_reason reason)
504	684	{
505	685	bool boot = false;
	686	+
506	687	sink_caps->signal = link_detect_sink(link, reason);
507	688	sink_caps->transaction_type =
508	689	get_ddc_transaction_type(sink_caps->signal);
..	..	@@ -511,15 +692,19 @@
511	692	sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
512	693	if (!detect_dp_sink_caps(link))
513	694	return false;
514		-
515	695	if (is_mst_supported(link)) {
516	696	sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
517	697	link->type = dc_connection_mst_branch;
518	698
519		- dal_ddc_service_set_transaction_type(
520		- link->ddc,
521		- sink_caps->transaction_type);
	699	+ dal_ddc_service_set_transaction_type(link->ddc,
	700	+ sink_caps->transaction_type);
522	701
	702	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	703	+ /* In case of fallback to SST when topology discovery below fails
	704	+ * HDCP caps will be querried again later by the upper layer (caller
	705	+ * of this function). */
	706	+ query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
	707	+#endif
523	708	/*
524	709	* This call will initiate MST topology discovery. Which
525	710	* will detect MST ports and add new DRM connector DRM
..	..	@@ -547,13 +732,10 @@
547	732	if (reason == DETECT_REASON_BOOT)
548	733	boot = true;
549	734
550		- dm_helpers_dp_update_branch_info(
551		- link->ctx,
552		- link);
	735	+ dm_helpers_dp_update_branch_info(link->ctx, link);
553	736
554		- if (!dm_helpers_dp_mst_start_top_mgr(
555		- link->ctx,
556		- link, boot)) {
	737	+ if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
	738	+ link, boot)) {
557	739	/* MST not supported */
558	740	link->type = dc_connection_single;
559	741	sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
..	..	@@ -561,7 +743,7 @@
561	743	}
562	744
563	745	if (link->type != dc_connection_mst_branch &&
564		- is_dp_active_dongle(link)) {
	746	+ is_dp_active_dongle(link)) {
565	747	/* DP active dongles */
566	748	link->type = dc_connection_active_dongle;
567	749	if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
..	..	@@ -572,14 +754,16 @@
572	754	return true;
573	755	}
574	756
575		- if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
	757	+ if (link->dpcd_caps.dongle_type !=
	758	+ DISPLAY_DONGLE_DP_HDMI_CONVERTER)
576	759	*converter_disable_audio = true;
577	760	}
578	761	} else {
579	762	/* DP passive dongles */
580	763	sink_caps->signal = dp_passive_dongle_detection(link->ddc,
581		- sink_caps,
582		- audio_support);
	764	+ sink_caps,
	765	+ audio_support);
	766	+ link->dpcd_caps.dongle_type = sink_caps->dongle_type;
583	767	}
584	768
585	769	return true;
..	..	@@ -593,10 +777,69 @@
593	777	if (new_edid->length == 0)
594	778	return false;
595	779
596		- return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
	780	+ return (memcmp(old_edid->raw_edid,
	781	+ new_edid->raw_edid, new_edid->length) == 0);
597	782	}
598	783
599		-bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
	784	+static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
	785	+{
	786	+ /**
	787	+ * something is terribly wrong if time out is > 200ms. (5Hz)
	788	+ * 500 microseconds * 400 tries us 200 ms
	789	+ **/
	790	+ unsigned int sleep_time_in_microseconds = 500;
	791	+ unsigned int tries_allowed = 400;
	792	+ bool is_in_alt_mode;
	793	+ unsigned long long enter_timestamp;
	794	+ unsigned long long finish_timestamp;
	795	+ unsigned long long time_taken_in_ns;
	796	+ int tries_taken;
	797	+
	798	+ DC_LOGGER_INIT(link->ctx->logger);
	799	+
	800	+ if (!link->link_enc->funcs->is_in_alt_mode)
	801	+ return true;
	802	+
	803	+ is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
	804	+ DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
	805	+
	806	+ if (is_in_alt_mode)
	807	+ return true;
	808	+
	809	+ enter_timestamp = dm_get_timestamp(link->ctx);
	810	+
	811	+ for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
	812	+ udelay(sleep_time_in_microseconds);
	813	+ /* ask the link if alt mode is enabled, if so return ok */
	814	+ if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
	815	+ finish_timestamp = dm_get_timestamp(link->ctx);
	816	+ time_taken_in_ns =
	817	+ dm_get_elapse_time_in_ns(link->ctx,
	818	+ finish_timestamp,
	819	+ enter_timestamp);
	820	+ DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
	821	+ div_u64(time_taken_in_ns, 1000000));
	822	+ return true;
	823	+ }
	824	+ }
	825	+ finish_timestamp = dm_get_timestamp(link->ctx);
	826	+ time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
	827	+ enter_timestamp);
	828	+ DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
	829	+ div_u64(time_taken_in_ns, 1000000));
	830	+ return false;
	831	+}
	832	+
	833	+/**
	834	+ * dc_link_detect() - Detect if a sink is attached to a given link
	835	+ *
	836	+ * link->local_sink is created or destroyed as needed.
	837	+ *
	838	+ * This does not create remote sinks but will trigger DM
	839	+ * to start MST detection if a branch is detected.
	840	+ */
	841	+static bool dc_link_detect_helper(struct dc_link *link,
	842	+ enum dc_detect_reason reason)
600	843	{
601	844	struct dc_sink_init_data sink_init_data = { 0 };
602	845	struct display_sink_capability sink_caps = { 0 };
..	..	@@ -611,28 +854,43 @@
611	854	struct dpcd_caps prev_dpcd_caps;
612	855	bool same_dpcd = true;
613	856	enum dc_connection_type new_connection_type = dc_connection_none;
	857	+ bool perform_dp_seamless_boot = false;
	858	+ const uint32_t post_oui_delay = 30; // 30ms
	859	+
614	860	DC_LOGGER_INIT(link->ctx->logger);
615		- if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
	861	+
	862	+ if (dc_is_virtual_signal(link->connector_signal))
616	863	return false;
617	864
618		- if (false == dc_link_detect_sink(link, &new_connection_type)) {
	865	+ if ((link->connector_signal == SIGNAL_TYPE_LVDS \|\|
	866	+ link->connector_signal == SIGNAL_TYPE_EDP) &&
	867	+ link->local_sink) {
	868	+ // need to re-write OUI and brightness in resume case
	869	+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
	870	+ dpcd_set_source_specific_data(link);
	871	+ msleep(post_oui_delay);
	872	+ dc_link_set_default_brightness_aux(link);
	873	+ //TODO: use cached
	874	+ }
	875	+
	876	+ return true;
	877	+ }
	878	+
	879	+ if (!dc_link_detect_sink(link, &new_connection_type)) {
619	880	BREAK_TO_DEBUGGER();
620	881	return false;
621	882	}
622	883
623		- if (link->connector_signal == SIGNAL_TYPE_EDP &&
624		- link->local_sink)
625		- return true;
626		-
627	884	prev_sink = link->local_sink;
628		- if (prev_sink != NULL) {
	885	+ if (prev_sink) {
629	886	dc_sink_retain(prev_sink);
630	887	memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
631	888	}
632		- link_disconnect_sink(link);
633	889
	890	+ link_disconnect_sink(link);
634	891	if (new_connection_type != dc_connection_none) {
635	892	link->type = new_connection_type;
	893	+ link->link_state_valid = false;
636	894
637	895	/* From Disconnected-to-Connected. */
638	896	switch (link->connector_signal) {
..	..	@@ -657,51 +915,77 @@
657	915	break;
658	916	}
659	917
	918	+ case SIGNAL_TYPE_LVDS: {
	919	+ sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
	920	+ sink_caps.signal = SIGNAL_TYPE_LVDS;
	921	+ break;
	922	+ }
	923	+
660	924	case SIGNAL_TYPE_EDP: {
	925	+ read_current_link_settings_on_detect(link);
	926	+
661	927	detect_edp_sink_caps(link);
662		- sink_caps.transaction_type =
663		- DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
	928	+ read_current_link_settings_on_detect(link);
	929	+ sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
664	930	sink_caps.signal = SIGNAL_TYPE_EDP;
665	931	break;
666	932	}
667	933
668	934	case SIGNAL_TYPE_DISPLAY_PORT: {
669		- if (!detect_dp(
670		- link,
671		- &sink_caps,
672		- &converter_disable_audio,
673		- aud_support, reason)) {
674		- if (prev_sink != NULL)
	935	+ /* wa HPD high coming too early*/
	936	+ if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
	937	+ /* if alt mode times out, return false */
	938	+ if (!wait_for_entering_dp_alt_mode(link))
	939	+ return false;
	940	+ }
	941	+
	942	+ if (!detect_dp(link, &sink_caps,
	943	+ &converter_disable_audio,
	944	+ aud_support, reason)) {
	945	+ if (prev_sink)
675	946	dc_sink_release(prev_sink);
676	947	return false;
677	948	}
678	949
679	950	// Check if dpcp block is the same
680		- if (prev_sink != NULL) {
681		- if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
	951	+ if (prev_sink) {
	952	+ if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
	953	+ sizeof(struct dpcd_caps)))
682	954	same_dpcd = false;
683	955	}
684		- /* Active dongle downstream unplug */
685		- if (link->type == dc_connection_active_dongle
686		- && link->dpcd_caps.sink_count.
687		- bits.SINK_COUNT == 0) {
688		- if (prev_sink != NULL)
	956	+ /* Active dongle downstream unplug*/
	957	+ if (link->type == dc_connection_active_dongle &&
	958	+ link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
	959	+ if (prev_sink)
	960	+ /* Downstream unplug */
689	961	dc_sink_release(prev_sink);
690	962	return true;
691	963	}
692	964
693	965	if (link->type == dc_connection_mst_branch) {
694	966	LINK_INFO("link=%d, mst branch is now Connected\n",
695		- link->link_index);
	967	+ link->link_index);
696	968	/* Need to setup mst link_cap struct here
697	969	* otherwise dc_link_detect() will leave mst link_cap
698	970	* empty which leads to allocate_mst_payload() has "0"
699	971	* pbn_per_slot value leading to exception on dc_fixpt_div()
700	972	*/
701		- link->verified_link_cap = link->reported_link_cap;
702		- if (prev_sink != NULL)
	973	+ dp_verify_mst_link_cap(link);
	974	+
	975	+ if (prev_sink)
703	976	dc_sink_release(prev_sink);
704	977	return false;
	978	+ }
	979	+
	980	+ // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
	981	+ if (reason == DETECT_REASON_BOOT &&
	982	+ !dc_ctx->dc->config.power_down_display_on_boot &&
	983	+ link->link_status.link_active)
	984	+ perform_dp_seamless_boot = true;
	985	+
	986	+ if (perform_dp_seamless_boot) {
	987	+ read_current_link_settings_on_detect(link);
	988	+ link->verified_link_cap = link->reported_link_cap;
705	989	}
706	990
707	991	break;
..	..	@@ -709,24 +993,23 @@
709	993
710	994	default:
711	995	DC_ERROR("Invalid connector type! signal:%d\n",
712		- link->connector_signal);
713		- if (prev_sink != NULL)
	996	+ link->connector_signal);
	997	+ if (prev_sink)
714	998	dc_sink_release(prev_sink);
715	999	return false;
716	1000	} /* switch() */
717	1001
718	1002	if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
719		- link->dpcd_sink_count = link->dpcd_caps.sink_count.
720		- bits.SINK_COUNT;
	1003	+ link->dpcd_sink_count =
	1004	+ link->dpcd_caps.sink_count.bits.SINK_COUNT;
721	1005	else
722	1006	link->dpcd_sink_count = 1;
723	1007
724		- dal_ddc_service_set_transaction_type(
725		- link->ddc,
726		- sink_caps.transaction_type);
	1008	+ dal_ddc_service_set_transaction_type(link->ddc,
	1009	+ sink_caps.transaction_type);
727	1010
728		- link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
729		- link->ddc);
	1011	+ link->aux_mode =
	1012	+ dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
730	1013
731	1014	sink_init_data.link = link;
732	1015	sink_init_data.sink_signal = sink_caps.signal;
..	..	@@ -734,20 +1017,19 @@
734	1017	sink = dc_sink_create(&sink_init_data);
735	1018	if (!sink) {
736	1019	DC_ERROR("Failed to create sink!\n");
737		- if (prev_sink != NULL)
	1020	+ if (prev_sink)
738	1021	dc_sink_release(prev_sink);
739	1022	return false;
740	1023	}
741	1024
742		- sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
	1025	+ sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
743	1026	sink->converter_disable_audio = converter_disable_audio;
744	1027
	1028	+ /* dc_sink_create returns a new reference */
745	1029	link->local_sink = sink;
746	1030
747		- edid_status = dm_helpers_read_local_edid(
748		- link->ctx,
749		- link,
750		- sink);
	1031	+ edid_status = dm_helpers_read_local_edid(link->ctx,
	1032	+ link, sink);
751	1033
752	1034	switch (edid_status) {
753	1035	case EDID_BAD_CHECKSUM:
..	..	@@ -755,7 +1037,6 @@
755	1037	break;
756	1038	case EDID_NO_RESPONSE:
757	1039	DC_LOG_ERROR("No EDID read.\n");
758		-
759	1040	/*
760	1041	* Abort detection for non-DP connectors if we have
761	1042	* no EDID
..	..	@@ -766,7 +1047,7 @@
766	1047	*/
767	1048	if (dc_is_hdmi_signal(link->connector_signal) \|\|
768	1049	dc_is_dvi_signal(link->connector_signal)) {
769		- if (prev_sink != NULL)
	1050	+ if (prev_sink)
770	1051	dc_sink_release(prev_sink);
771	1052	link_disconnect_sink(link);
772	1053
..	..	@@ -793,50 +1074,57 @@
793	1074	break;
794	1075	}
795	1076
	1077	+ if (link->local_sink->edid_caps.panel_patch.disable_fec)
	1078	+ link->ctx->dc->debug.disable_fec = true;
	1079	+
796	1080	// Check if edid is the same
797		- if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) \|\| (edid_status == EDID_OK)))
798		- same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
	1081	+ if ((prev_sink) &&
	1082	+ (edid_status == EDID_THE_SAME \|\| edid_status == EDID_OK))
	1083	+ same_edid = is_same_edid(&prev_sink->dc_edid,
	1084	+ &sink->dc_edid);
	1085	+
	1086	+ if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
	1087	+ link->ctx->dc->debug.hdmi20_disable = true;
799	1088
800	1089	if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
801		- sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
	1090	+ sink_caps.transaction_type ==
	1091	+ DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
802	1092	/*
803	1093	* TODO debug why Dell 2413 doesn't like
804	1094	* two link trainings
805	1095	*/
	1096	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	1097	+ query_hdcp_capability(sink->sink_signal, link);
	1098	+#endif
806	1099
807		- /* deal with non-mst cases */
808		- for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
809		- int fail_count = 0;
810		-
811		- dp_verify_link_cap(link,
812		- &link->reported_link_cap,
813		- &fail_count);
814		-
815		- if (fail_count == 0)
816		- break;
817		- }
818		-
	1100	+ // verify link cap for SST non-seamless boot
	1101	+ if (!perform_dp_seamless_boot)
	1102	+ dp_verify_link_cap_with_retries(link,
	1103	+ &link->reported_link_cap,
	1104	+ LINK_TRAINING_MAX_VERIFY_RETRY);
819	1105	} else {
820	1106	// If edid is the same, then discard new sink and revert back to original sink
821	1107	if (same_edid) {
822	1108	link_disconnect_remap(prev_sink, link);
823	1109	sink = prev_sink;
824	1110	prev_sink = NULL;
825		-
826	1111	}
	1112	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	1113	+ query_hdcp_capability(sink->sink_signal, link);
	1114	+#endif
827	1115	}
828	1116
829	1117	/* HDMI-DVI Dongle */
830	1118	if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
831		- !sink->edid_caps.edid_hdmi)
	1119	+ !sink->edid_caps.edid_hdmi)
832	1120	sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
833	1121
834	1122	/* Connectivity log: detection */
835		- for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
	1123	+ for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
836	1124	CONN_DATA_DETECT(link,
837		- &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
838		- EDID_BLOCK_SIZE,
839		- "%s: [Block %d] ", sink->edid_caps.display_name, i);
	1125	+ &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
	1126	+ DC_EDID_BLOCK_SIZE,
	1127	+ "%s: [Block %d] ", sink->edid_caps.display_name, i);
840	1128	}
841	1129
842	1130	DC_LOG_DETECTION_EDID_PARSER("%s: "
..	..	@@ -871,42 +1159,76 @@
871	1159	sink->edid_caps.audio_modes[i].sample_rate,
872	1160	sink->edid_caps.audio_modes[i].sample_size);
873	1161	}
874		-
875	1162	} else {
876	1163	/* From Connected-to-Disconnected. */
877	1164	if (link->type == dc_connection_mst_branch) {
878	1165	LINK_INFO("link=%d, mst branch is now Disconnected\n",
879		- link->link_index);
	1166	+ link->link_index);
880	1167
881	1168	dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
882	1169
883	1170	link->mst_stream_alloc_table.stream_count = 0;
884		- memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
	1171	+ memset(link->mst_stream_alloc_table.stream_allocations,
	1172	+ 0,
	1173	+ sizeof(link->mst_stream_alloc_table.stream_allocations));
885	1174	}
886	1175
887	1176	link->type = dc_connection_none;
888	1177	sink_caps.signal = SIGNAL_TYPE_NONE;
	1178	+ /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
	1179	+ * is not cleared. If we emulate a DP signal on this connection, it thinks
	1180	+ * the dongle is still there and limits the number of modes we can emulate.
	1181	+ * Clear dongle_max_pix_clk on disconnect to fix this
	1182	+ */
	1183	+ link->dongle_max_pix_clk = 0;
889	1184	}
890	1185
891	1186	LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
892		- link->link_index, sink,
893		- (sink_caps.signal == SIGNAL_TYPE_NONE ?
894		- "Disconnected":"Connected"), prev_sink,
895		- same_dpcd, same_edid);
	1187	+ link->link_index, sink,
	1188	+ (sink_caps.signal ==
	1189	+ SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
	1190	+ prev_sink, same_dpcd, same_edid);
896	1191
897		- if (prev_sink != NULL)
	1192	+ if (prev_sink)
898	1193	dc_sink_release(prev_sink);
899	1194
900	1195	return true;
901	1196	}
902	1197
903		-static enum hpd_source_id get_hpd_line(
904		- struct dc_link *link)
	1198	+bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
	1199	+{
	1200	+ const struct dc *dc = link->dc;
	1201	+ bool ret;
	1202	+
	1203	+ /* get out of low power state */
	1204	+ clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
	1205	+
	1206	+ ret = dc_link_detect_helper(link, reason);
	1207	+
	1208	+ /* Go back to power optimized state */
	1209	+ clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
	1210	+
	1211	+ return ret;
	1212	+}
	1213	+
	1214	+bool dc_link_get_hpd_state(struct dc_link *dc_link)
	1215	+{
	1216	+ uint32_t state;
	1217	+
	1218	+ dal_gpio_lock_pin(dc_link->hpd_gpio);
	1219	+ dal_gpio_get_value(dc_link->hpd_gpio, &state);
	1220	+ dal_gpio_unlock_pin(dc_link->hpd_gpio);
	1221	+
	1222	+ return state;
	1223	+}
	1224	+
	1225	+static enum hpd_source_id get_hpd_line(struct dc_link *link)
905	1226	{
906	1227	struct gpio *hpd;
907	1228	enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
908	1229
909		- hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
	1230	+ hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
	1231	+ link->ctx->gpio_service);
910	1232
911	1233	if (hpd) {
912	1234	switch (dal_irq_get_source(hpd)) {
..	..	@@ -981,8 +1303,7 @@
981	1303	return channel;
982	1304	}
983	1305
984		-static enum transmitter translate_encoder_to_transmitter(
985		- struct graphics_object_id encoder)
	1306	+static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
986	1307	{
987	1308	switch (encoder.id) {
988	1309	case ENCODER_ID_INTERNAL_UNIPHY:
..	..	@@ -1046,18 +1367,18 @@
1046	1367	}
1047	1368	}
1048	1369
1049		-static bool construct(
1050		- struct dc_link *link,
1051		- const struct link_init_data *init_params)
	1370	+static bool dc_link_construct(struct dc_link *link,
	1371	+ const struct link_init_data *init_params)
1052	1372	{
1053	1373	uint8_t i;
1054		- struct gpio *hpd_gpio = NULL;
1055	1374	struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1056	1375	struct dc_context *dc_ctx = init_params->ctx;
1057	1376	struct encoder_init_data enc_init_data = { 0 };
	1377	+ struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1058	1378	struct integrated_info info = {{{ 0 }}};
1059	1379	struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1060	1380	const struct dc_vbios_funcs *bp_funcs = bios->funcs;
	1381	+
1061	1382	DC_LOGGER_INIT(dc_ctx->logger);
1062	1383
1063	1384	link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
..	..	@@ -1069,22 +1390,31 @@
1069	1390	link->ctx = dc_ctx;
1070	1391	link->link_index = init_params->link_index;
1071	1392
1072		- link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
	1393	+ memset(&link->preferred_training_settings, 0,
	1394	+ sizeof(struct dc_link_training_overrides));
	1395	+ memset(&link->preferred_link_setting, 0,
	1396	+ sizeof(struct dc_link_settings));
	1397	+
	1398	+ link->link_id =
	1399	+ bios->funcs->get_connector_id(bios, init_params->connector_index);
1073	1400
1074	1401	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1075		- dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1076		- __func__, init_params->connector_index,
1077		- link->link_id.type, OBJECT_TYPE_CONNECTOR);
	1402	+ dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
	1403	+ __func__, init_params->connector_index,
	1404	+ link->link_id.type, OBJECT_TYPE_CONNECTOR);
1078	1405	goto create_fail;
1079	1406	}
1080	1407
1081	1408	if (link->dc->res_pool->funcs->link_init)
1082	1409	link->dc->res_pool->funcs->link_init(link);
1083	1410
1084		- hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1085		-
1086		- if (hpd_gpio != NULL)
1087		- link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
	1411	+ link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
	1412	+ link->ctx->gpio_service);
	1413	+ if (link->hpd_gpio) {
	1414	+ dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
	1415	+ dal_gpio_unlock_pin(link->hpd_gpio);
	1416	+ link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
	1417	+ }
1088	1418
1089	1419	switch (link->link_id.id) {
1090	1420	case CONNECTOR_ID_HDMI_TYPE_A:
..	..	@@ -1100,44 +1430,44 @@
1100	1430	link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1101	1431	break;
1102	1432	case CONNECTOR_ID_DISPLAY_PORT:
1103		- link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
	1433	+ link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1104	1434
1105		- if (hpd_gpio != NULL)
	1435	+ if (link->hpd_gpio)
1106	1436	link->irq_source_hpd_rx =
1107		- dal_irq_get_rx_source(hpd_gpio);
	1437	+ dal_irq_get_rx_source(link->hpd_gpio);
1108	1438
1109	1439	break;
1110	1440	case CONNECTOR_ID_EDP:
1111	1441	link->connector_signal = SIGNAL_TYPE_EDP;
1112	1442
1113		- if (hpd_gpio != NULL) {
	1443	+ if (link->hpd_gpio) {
1114	1444	link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1115	1445	link->irq_source_hpd_rx =
1116		- dal_irq_get_rx_source(hpd_gpio);
	1446	+ dal_irq_get_rx_source(link->hpd_gpio);
1117	1447	}
	1448	+
	1449	+ break;
	1450	+ case CONNECTOR_ID_LVDS:
	1451	+ link->connector_signal = SIGNAL_TYPE_LVDS;
1118	1452	break;
1119	1453	default:
1120		- DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
	1454	+ DC_LOG_WARNING("Unsupported Connector type:%d!\n",
	1455	+ link->link_id.id);
1121	1456	goto create_fail;
1122		- }
1123		-
1124		- if (hpd_gpio != NULL) {
1125		- dal_gpio_destroy_irq(&hpd_gpio);
1126		- hpd_gpio = NULL;
1127	1457	}
1128	1458
1129	1459	/* TODO: #DAL3 Implement id to str function.*/
1130	1460	LINK_INFO("Connector[%d] description:"
1131		- "signal %d\n",
1132		- init_params->connector_index,
1133		- link->connector_signal);
	1461	+ "signal %d\n",
	1462	+ init_params->connector_index,
	1463	+ link->connector_signal);
1134	1464
1135	1465	ddc_service_init_data.ctx = link->ctx;
1136	1466	ddc_service_init_data.id = link->link_id;
1137	1467	ddc_service_init_data.link = link;
1138	1468	link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1139	1469
1140		- if (link->ddc == NULL) {
	1470	+ if (!link->ddc) {
1141	1471	DC_ERROR("Failed to create ddc_service!\n");
1142	1472	goto ddc_create_fail;
1143	1473	}
..	..	@@ -1148,11 +1478,27 @@
1148	1478	}
1149	1479
1150	1480	link->ddc_hw_inst =
1151		- dal_ddc_get_line(
1152		- dal_ddc_service_get_ddc_pin(link->ddc));
	1481	+ dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
	1482	+
	1483	+
	1484	+ if (link->dc->res_pool->funcs->panel_cntl_create &&
	1485	+ (link->link_id.id == CONNECTOR_ID_EDP \|\|
	1486	+ link->link_id.id == CONNECTOR_ID_LVDS)) {
	1487	+ panel_cntl_init_data.ctx = dc_ctx;
	1488	+ panel_cntl_init_data.inst = 0;
	1489	+ link->panel_cntl =
	1490	+ link->dc->res_pool->funcs->panel_cntl_create(
	1491	+ &panel_cntl_init_data);
	1492	+
	1493	+ if (link->panel_cntl == NULL) {
	1494	+ DC_ERROR("Failed to create link panel_cntl!\n");
	1495	+ goto panel_cntl_create_fail;
	1496	+ }
	1497	+ }
1153	1498
1154	1499	enc_init_data.ctx = dc_ctx;
1155		- bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
	1500	+ bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
	1501	+ &enc_init_data.encoder);
1156	1502	enc_init_data.connector = link->link_id;
1157	1503	enc_init_data.channel = get_ddc_line(link);
1158	1504	enc_init_data.hpd_source = get_hpd_line(link);
..	..	@@ -1160,11 +1506,11 @@
1160	1506	link->hpd_src = enc_init_data.hpd_source;
1161	1507
1162	1508	enc_init_data.transmitter =
1163		- translate_encoder_to_transmitter(enc_init_data.encoder);
1164		- link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1165		- &enc_init_data);
	1509	+ translate_encoder_to_transmitter(enc_init_data.encoder);
	1510	+ link->link_enc =
	1511	+ link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1166	1512
1167		- if( link->link_enc == NULL) {
	1513	+ if (!link->link_enc) {
1168	1514	DC_ERROR("Failed to create link encoder!\n");
1169	1515	goto link_enc_create_fail;
1170	1516	}
..	..	@@ -1172,8 +1518,9 @@
1172	1518	link->link_enc_hw_inst = link->link_enc->transmitter;
1173	1519
1174	1520	for (i = 0; i < 4; i++) {
1175		- if (BP_RESULT_OK !=
1176		- bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
	1521	+ if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
	1522	+ link->link_id, i,
	1523	+ &link->device_tag) != BP_RESULT_OK) {
1177	1524	DC_ERROR("Failed to find device tag!\n");
1178	1525	goto device_tag_fail;
1179	1526	}
..	..	@@ -1181,13 +1528,14 @@
1181	1528	/* Look for device tag that matches connector signal,
1182	1529	* CRT for rgb, LCD for other supported signal tyes
1183	1530	*/
1184		- if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
	1531	+ if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
	1532	+ link->device_tag.dev_id))
1185	1533	continue;
1186		- if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1187		- && link->connector_signal != SIGNAL_TYPE_RGB)
	1534	+ if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
	1535	+ link->connector_signal != SIGNAL_TYPE_RGB)
1188	1536	continue;
1189		- if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1190		- && link->connector_signal == SIGNAL_TYPE_RGB)
	1537	+ if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
	1538	+ link->connector_signal == SIGNAL_TYPE_RGB)
1191	1539	continue;
1192	1540	break;
1193	1541	}
..	..	@@ -1199,22 +1547,25 @@
1199	1547	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1200	1548	struct external_display_path *path =
1201	1549	&info.ext_disp_conn_info.path[i];
1202		- if (path->device_connector_id.enum_id == link->link_id.enum_id
1203		- && path->device_connector_id.id == link->link_id.id
1204		- && path->device_connector_id.type == link->link_id.type) {
1205	1550
1206		- if (link->device_tag.acpi_device != 0
1207		- && path->device_acpi_enum == link->device_tag.acpi_device) {
	1551	+ if (path->device_connector_id.enum_id == link->link_id.enum_id &&
	1552	+ path->device_connector_id.id == link->link_id.id &&
	1553	+ path->device_connector_id.type == link->link_id.type) {
	1554	+ if (link->device_tag.acpi_device != 0 &&
	1555	+ path->device_acpi_enum == link->device_tag.acpi_device) {
1208	1556	link->ddi_channel_mapping = path->channel_mapping;
1209	1557	link->chip_caps = path->caps;
1210	1558	} else if (path->device_tag ==
1211		- link->device_tag.dev_id.raw_device_tag) {
	1559	+ link->device_tag.dev_id.raw_device_tag) {
1212	1560	link->ddi_channel_mapping = path->channel_mapping;
1213	1561	link->chip_caps = path->caps;
1214	1562	}
1215	1563	break;
1216	1564	}
1217	1565	}
	1566	+
	1567	+ if (bios->funcs->get_atom_dc_golden_table)
	1568	+ bios->funcs->get_atom_dc_golden_table(bios);
1218	1569
1219	1570	/*
1220	1571	* TODO check if GPIO programmed correctly
..	..	@@ -1224,16 +1575,22 @@
1224	1575	*/
1225	1576	program_hpd_filter(link);
1226	1577
	1578	+ link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
	1579	+
1227	1580	return true;
1228	1581	device_tag_fail:
1229	1582	link->link_enc->funcs->destroy(&link->link_enc);
1230	1583	link_enc_create_fail:
	1584	+ if (link->panel_cntl != NULL)
	1585	+ link->panel_cntl->funcs->destroy(&link->panel_cntl);
	1586	+panel_cntl_create_fail:
1231	1587	dal_ddc_service_destroy(&link->ddc);
1232	1588	ddc_create_fail:
1233	1589	create_fail:
1234	1590
1235		- if (hpd_gpio != NULL) {
1236		- dal_gpio_destroy_irq(&hpd_gpio);
	1591	+ if (link->hpd_gpio) {
	1592	+ dal_gpio_destroy_irq(&link->hpd_gpio);
	1593	+ link->hpd_gpio = NULL;
1237	1594	}
1238	1595
1239	1596	return false;
..	..	@@ -1250,7 +1607,7 @@
1250	1607	if (NULL == link)
1251	1608	goto alloc_fail;
1252	1609
1253		- if (false == construct(link, init_params))
	1610	+ if (false == dc_link_construct(link, init_params))
1254	1611	goto construct_fail;
1255	1612
1256	1613	return link;
..	..	@@ -1264,66 +1621,15 @@
1264	1621
1265	1622	void link_destroy(struct dc_link **link)
1266	1623	{
1267		- destruct(*link);
	1624	+ dc_link_destruct(*link);
1268	1625	kfree(*link);
1269	1626	*link = NULL;
1270		-}
1271		-
1272		-static void dpcd_configure_panel_mode(
1273		- struct dc_link *link,
1274		- enum dp_panel_mode panel_mode)
1275		-{
1276		- union dpcd_edp_config edp_config_set;
1277		- bool panel_mode_edp = false;
1278		- DC_LOGGER_INIT(link->ctx->logger);
1279		-
1280		- memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1281		-
1282		- if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1283		-
1284		- switch (panel_mode) {
1285		- case DP_PANEL_MODE_EDP:
1286		- case DP_PANEL_MODE_SPECIAL:
1287		- panel_mode_edp = true;
1288		- break;
1289		-
1290		- default:
1291		- break;
1292		- }
1293		-
1294		- /set edp panel mode in receiver/
1295		- core_link_read_dpcd(
1296		- link,
1297		- DP_EDP_CONFIGURATION_SET,
1298		- &edp_config_set.raw,
1299		- sizeof(edp_config_set.raw));
1300		-
1301		- if (edp_config_set.bits.PANEL_MODE_EDP
1302		- != panel_mode_edp) {
1303		- enum ddc_result result = DDC_RESULT_UNKNOWN;
1304		-
1305		- edp_config_set.bits.PANEL_MODE_EDP =
1306		- panel_mode_edp;
1307		- result = core_link_write_dpcd(
1308		- link,
1309		- DP_EDP_CONFIGURATION_SET,
1310		- &edp_config_set.raw,
1311		- sizeof(edp_config_set.raw));
1312		-
1313		- ASSERT(result == DDC_RESULT_SUCESSFULL);
1314		- }
1315		- }
1316		- DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1317		- "eDP panel mode enabled: %d \n",
1318		- link->link_index,
1319		- link->dpcd_caps.panel_mode_edp,
1320		- panel_mode_edp);
1321	1627	}
1322	1628
1323	1629	static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1324	1630	{
1325	1631	struct dc_stream_state *stream = pipe_ctx->stream;
1326		- struct dc_link *link = stream->sink->link;
	1632	+ struct dc_link *link = stream->link;
1327	1633	union down_spread_ctrl old_downspread;
1328	1634	union down_spread_ctrl new_downspread;
1329	1635
..	..	@@ -1341,71 +1647,80 @@
1341	1647	}
1342	1648	}
1343	1649
1344		-static enum dc_status enable_link_dp(
1345		- struct dc_state *state,
1346		- struct pipe_ctx *pipe_ctx)
	1650	+static enum dc_status enable_link_dp(struct dc_state *state,
	1651	+ struct pipe_ctx *pipe_ctx)
1347	1652	{
1348	1653	struct dc_stream_state *stream = pipe_ctx->stream;
1349	1654	enum dc_status status;
1350	1655	bool skip_video_pattern;
1351		- struct dc_link *link = stream->sink->link;
	1656	+ struct dc_link *link = stream->link;
1352	1657	struct dc_link_settings link_settings = {0};
1353		- enum dp_panel_mode panel_mode;
1354		- enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
	1658	+ bool fec_enable;
	1659	+ int i;
	1660	+ bool apply_seamless_boot_optimization = false;
	1661	+ uint32_t bl_oled_enable_delay = 50; // in ms
	1662	+ const uint32_t post_oui_delay = 30; // 30ms
	1663	+
	1664	+ // check for seamless boot
	1665	+ for (i = 0; i < state->stream_count; i++) {
	1666	+ if (state->streams[i]->apply_seamless_boot_optimization) {
	1667	+ apply_seamless_boot_optimization = true;
	1668	+ break;
	1669	+ }
	1670	+ }
1355	1671
1356	1672	/* get link settings for video mode timing */
1357	1673	decide_link_settings(stream, &link_settings);
1358	1674
1359		- /* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
1360		- * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
1361		- */
1362		- if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1363		- max_link_rate = LINK_RATE_HIGH3;
1364		-
1365		- if (link_settings.link_rate == max_link_rate) {
1366		- struct dc_clocks clocks = state->bw.dcn.clk;
1367		-
1368		- /* dce/dcn compat, do not update dispclk */
1369		- clocks.dispclk_khz = 0;
1370		- /* 27mhz = 27000000hz= 27000khz */
1371		- clocks.phyclk_khz = link_settings.link_rate * 27000;
1372		-
1373		- state->dis_clk->funcs->update_clocks(
1374		- state->dis_clk, &clocks, false);
	1675	+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
	1676	+ /in case it is not on/
	1677	+ link->dc->hwss.edp_power_control(link, true);
	1678	+ link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1375	1679	}
1376	1680
1377		- dp_enable_link_phy(
1378		- link,
1379		- pipe_ctx->stream->signal,
1380		- pipe_ctx->clock_source->id,
1381		- &link_settings);
	1681	+ pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
	1682	+ link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
	1683	+ if (state->clk_mgr && !apply_seamless_boot_optimization)
	1684	+ state->clk_mgr->funcs->update_clocks(state->clk_mgr,
	1685	+ state, false);
1382	1686
1383		- if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1384		- int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1385		-
1386		- msleep(delay_dp_power_up_in_ms);
1387		- }
1388		-
1389		- panel_mode = dp_get_panel_mode(link);
1390		- dpcd_configure_panel_mode(link, panel_mode);
	1687	+ // during mode switch we do DP_SET_POWER off then on, and OUI is lost
	1688	+ dpcd_set_source_specific_data(link);
	1689	+ if (link->dpcd_sink_ext_caps.raw != 0)
	1690	+ msleep(post_oui_delay);
1391	1691
1392	1692	skip_video_pattern = true;
1393	1693
1394	1694	if (link_settings.link_rate == LINK_RATE_LOW)
1395		- skip_video_pattern = false;
	1695	+ skip_video_pattern = false;
1396	1696
1397		- if (perform_link_training_with_retries(
1398		- link,
1399		- &link_settings,
1400		- skip_video_pattern,
1401		- LINK_TRAINING_ATTEMPTS)) {
	1697	+ if (perform_link_training_with_retries(&link_settings,
	1698	+ skip_video_pattern,
	1699	+ LINK_TRAINING_ATTEMPTS,
	1700	+ pipe_ctx,
	1701	+ pipe_ctx->stream->signal)) {
1402	1702	link->cur_link_settings = link_settings;
1403	1703	status = DC_OK;
1404		- }
1405		- else
	1704	+ } else {
1406	1705	status = DC_FAIL_DP_LINK_TRAINING;
	1706	+ }
1407	1707
1408		- enable_stream_features(pipe_ctx);
	1708	+ if (link->preferred_training_settings.fec_enable)
	1709	+ fec_enable = *link->preferred_training_settings.fec_enable;
	1710	+ else
	1711	+ fec_enable = true;
	1712	+
	1713	+ dp_set_fec_enable(link, fec_enable);
	1714	+
	1715	+ // during mode set we do DP_SET_POWER off then on, aux writes are lost
	1716	+ if (link->dpcd_sink_ext_caps.bits.oled == 1 \|\|
	1717	+ link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 \|\|
	1718	+ link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
	1719	+ dc_link_set_default_brightness_aux(link); // TODO: use cached if known
	1720	+ if (link->dpcd_sink_ext_caps.bits.oled == 1)
	1721	+ msleep(bl_oled_enable_delay);
	1722	+ dc_link_backlight_enable_aux(link, true);
	1723	+ }
1409	1724
1410	1725	return status;
1411	1726	}
..	..	@@ -1415,14 +1730,8 @@
1415	1730	struct pipe_ctx *pipe_ctx)
1416	1731	{
1417	1732	enum dc_status status;
1418		- struct dc_stream_state *stream = pipe_ctx->stream;
1419		- struct dc_link *link = stream->sink->link;
1420		- /in case it is not on/
1421		- link->dc->hwss.edp_power_control(link, true);
1422		- link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1423	1733
1424	1734	status = enable_link_dp(state, pipe_ctx);
1425		-
1426	1735
1427	1736	return status;
1428	1737	}
..	..	@@ -1431,7 +1740,7 @@
1431	1740	struct dc_state *state,
1432	1741	struct pipe_ctx *pipe_ctx)
1433	1742	{
1434		- struct dc_link *link = pipe_ctx->stream->sink->link;
	1743	+ struct dc_link *link = pipe_ctx->stream->link;
1435	1744
1436	1745	/* sink signal type after MST branch is MST. Multiple MST sinks
1437	1746	* share one link. Link DP PHY is enable or training only once.
..	..	@@ -1441,6 +1750,11 @@
1441	1750
1442	1751	/* clear payload table */
1443	1752	dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
	1753	+
	1754	+ /* to make sure the pending down rep can be processed
	1755	+ * before enabling the link
	1756	+ */
	1757	+ dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1444	1758
1445	1759	/* set the sink to MST mode before enabling the link */
1446	1760	dp_enable_mst_on_sink(link, true);
..	..	@@ -1564,8 +1878,8 @@
1564	1878	payload.write = true;
1565	1879	cmd.payloads = &payload;
1566	1880
1567		- if (dc_submit_i2c(pipe_ctx->stream->ctx->dc,
1568		- pipe_ctx->stream->sink->link->link_index, &cmd))
	1881	+ if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
	1882	+ pipe_ctx->stream->link, &cmd))
1569	1883	return true;
1570	1884
1571	1885	return false;
..	..	@@ -1584,6 +1898,7 @@
1584	1898	uint8_t value = 0;
1585	1899	int i = 0;
1586	1900	bool i2c_success = false;
	1901	+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1587	1902
1588	1903	memset(&buffer, 0, sizeof(buffer));
1589	1904
..	..	@@ -1597,6 +1912,9 @@
1597	1912	buffer[1] = settings->reg_settings[i].i2c_reg_val;
1598	1913	i2c_success = i2c_write(pipe_ctx, slave_address,
1599	1914	buffer, sizeof(buffer));
	1915	+ RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
	1916	+ offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
	1917	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1600	1918
1601	1919	if (!i2c_success)
1602	1920	goto i2c_write_fail;
..	..	@@ -1614,7 +1932,7 @@
1614	1932	else {
1615	1933	i2c_success =
1616	1934	dal_ddc_service_query_ddc_data(
1617		- pipe_ctx->stream->sink->link->ddc,
	1935	+ pipe_ctx->stream->link->ddc,
1618	1936	slave_address, &offset, 1, &value, 1);
1619	1937	if (!i2c_success)
1620	1938	goto i2c_write_fail;
..	..	@@ -1625,6 +1943,9 @@
1625	1943	buffer[1] = value \| apply_rx_tx_change;
1626	1944	i2c_success = i2c_write(pipe_ctx, slave_address,
1627	1945	buffer, sizeof(buffer));
	1946	+ RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
	1947	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	1948	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1628	1949	if (!i2c_success)
1629	1950	goto i2c_write_fail;
1630	1951	}
..	..	@@ -1641,6 +1962,9 @@
1641	1962	buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1642	1963	i2c_success = i2c_write(pipe_ctx, slave_address,
1643	1964	buffer, sizeof(buffer));
	1965	+ RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
	1966	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	1967	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1644	1968
1645	1969	if (!i2c_success)
1646	1970	goto i2c_write_fail;
..	..	@@ -1658,7 +1982,7 @@
1658	1982	else {
1659	1983	i2c_success =
1660	1984	dal_ddc_service_query_ddc_data(
1661		- pipe_ctx->stream->sink->link->ddc,
	1985	+ pipe_ctx->stream->link->ddc,
1662	1986	slave_address, &offset, 1, &value, 1);
1663	1987	if (!i2c_success)
1664	1988	goto i2c_write_fail;
..	..	@@ -1669,6 +1993,9 @@
1669	1993	buffer[1] = value \| apply_rx_tx_change;
1670	1994	i2c_success = i2c_write(pipe_ctx, slave_address,
1671	1995	buffer, sizeof(buffer));
	1996	+ RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
	1997	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	1998	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1672	1999	if (!i2c_success)
1673	2000	goto i2c_write_fail;
1674	2001	}
..	..	@@ -1684,6 +2011,9 @@
1684	2011	buffer[1] = 0x01;
1685	2012	i2c_success = i2c_write(pipe_ctx, slave_address,
1686	2013	buffer, sizeof(buffer));
	2014	+ RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
	2015	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2016	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1687	2017	if (!i2c_success)
1688	2018	goto i2c_write_fail;
1689	2019
..	..	@@ -1692,6 +2022,9 @@
1692	2022	buffer[1] = 0x23;
1693	2023	i2c_success = i2c_write(pipe_ctx, slave_address,
1694	2024	buffer, sizeof(buffer));
	2025	+ RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
	2026	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2027	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1695	2028	if (!i2c_success)
1696	2029	goto i2c_write_fail;
1697	2030
..	..	@@ -1700,6 +2033,9 @@
1700	2033	buffer[1] = 0x00;
1701	2034	i2c_success = i2c_write(pipe_ctx, slave_address,
1702	2035	buffer, sizeof(buffer));
	2036	+ RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
	2037	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2038	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1703	2039	if (!i2c_success)
1704	2040	goto i2c_write_fail;
1705	2041
..	..	@@ -1719,6 +2055,7 @@
1719	2055	uint8_t slave_address = (0xBA >> 1);
1720	2056	uint8_t buffer[2];
1721	2057	bool i2c_success = false;
	2058	+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1722	2059
1723	2060	memset(&buffer, 0, sizeof(buffer));
1724	2061
..	..	@@ -1728,6 +2065,9 @@
1728	2065	buffer[1] = 0x13;
1729	2066	i2c_success = i2c_write(pipe_ctx, slave_address,
1730	2067	buffer, sizeof(buffer));
	2068	+ RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
	2069	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2070	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1731	2071	if (!i2c_success)
1732	2072	goto i2c_write_fail;
1733	2073
..	..	@@ -1736,6 +2076,9 @@
1736	2076	buffer[1] = 0x17;
1737	2077	i2c_success = i2c_write(pipe_ctx, slave_address,
1738	2078	buffer, sizeof(buffer));
	2079	+ RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
	2080	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2081	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1739	2082	if (!i2c_success)
1740	2083	goto i2c_write_fail;
1741	2084
..	..	@@ -1744,6 +2087,9 @@
1744	2087	buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1745	2088	i2c_success = i2c_write(pipe_ctx, slave_address,
1746	2089	buffer, sizeof(buffer));
	2090	+ RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
	2091	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2092	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1747	2093	if (!i2c_success)
1748	2094	goto i2c_write_fail;
1749	2095
..	..	@@ -1752,6 +2098,9 @@
1752	2098	buffer[1] = 0x17;
1753	2099	i2c_success = i2c_write(pipe_ctx, slave_address,
1754	2100	buffer, sizeof(buffer));
	2101	+ RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
	2102	+ offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
	2103	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1755	2104	if (!i2c_success)
1756	2105	goto i2c_write_fail;
1757	2106
..	..	@@ -1760,6 +2109,9 @@
1760	2109	buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1761	2110	i2c_success = i2c_write(pipe_ctx, slave_address,
1762	2111	buffer, sizeof(buffer));
	2112	+ RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
	2113	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2114	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1763	2115	if (!i2c_success)
1764	2116	goto i2c_write_fail;
1765	2117
..	..	@@ -1768,6 +2120,9 @@
1768	2120	buffer[1] = 0x17;
1769	2121	i2c_success = i2c_write(pipe_ctx, slave_address,
1770	2122	buffer, sizeof(buffer));
	2123	+ RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
	2124	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2125	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1771	2126	if (!i2c_success)
1772	2127	goto i2c_write_fail;
1773	2128
..	..	@@ -1780,6 +2135,9 @@
1780	2135	buffer[1] = 0x01;
1781	2136	i2c_success = i2c_write(pipe_ctx, slave_address,
1782	2137	buffer, sizeof(buffer));
	2138	+ RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
	2139	+ offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
	2140	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1783	2141	if (!i2c_success)
1784	2142	goto i2c_write_fail;
1785	2143
..	..	@@ -1788,6 +2146,9 @@
1788	2146	buffer[1] = 0x23;
1789	2147	i2c_success = i2c_write(pipe_ctx, slave_address,
1790	2148	buffer, sizeof(buffer));
	2149	+ RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
	2150	+ offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
	2151	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1791	2152	if (!i2c_success)
1792	2153	goto i2c_write_fail;
1793	2154
..	..	@@ -1796,6 +2157,9 @@
1796	2157	buffer[1] = 0x00;
1797	2158	i2c_success = i2c_write(pipe_ctx, slave_address,
1798	2159	buffer, sizeof(buffer));
	2160	+ RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
	2161	+ offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
	2162	+ slave_address, buffer[0], buffer[1], i2c_success?1:0);
1799	2163	if (!i2c_success)
1800	2164	goto i2c_write_fail;
1801	2165	}
..	..	@@ -1813,6 +2177,7 @@
1813	2177	uint8_t slave_address = (0xF0 >> 1);
1814	2178	uint8_t buffer[16];
1815	2179	bool i2c_success = false;
	2180	+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1816	2181
1817	2182	memset(&buffer, 0, sizeof(buffer));
1818	2183
..	..	@@ -1824,15 +2189,59 @@
1824	2189
1825	2190	i2c_success = i2c_write(pipe_ctx, slave_address,
1826	2191	buffer, sizeof(buffer));
	2192	+ RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
	2193	+ \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
	2194	+ offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
	2195	+ i2c_success = %d\n",
	2196	+ slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
1827	2197
1828	2198	if (!i2c_success)
1829	2199	DC_LOG_DEBUG("Set redriver failed");
1830	2200	}
1831	2201
	2202	+static void disable_link(struct dc_link *link, enum signal_type signal)
	2203	+{
	2204	+ /*
	2205	+ * TODO: implement call for dp_set_hw_test_pattern
	2206	+ * it is needed for compliance testing
	2207	+ */
	2208	+
	2209	+ /* Here we need to specify that encoder output settings
	2210	+ * need to be calculated as for the set mode,
	2211	+ * it will lead to querying dynamic link capabilities
	2212	+ * which should be done before enable output
	2213	+ */
	2214	+
	2215	+ if (dc_is_dp_signal(signal)) {
	2216	+ /* SST DP, eDP */
	2217	+ if (dc_is_dp_sst_signal(signal))
	2218	+ dp_disable_link_phy(link, signal);
	2219	+ else
	2220	+ dp_disable_link_phy_mst(link, signal);
	2221	+
	2222	+ if (dc_is_dp_sst_signal(signal) \|\|
	2223	+ link->mst_stream_alloc_table.stream_count == 0) {
	2224	+ dp_set_fec_enable(link, false);
	2225	+ dp_set_fec_ready(link, false);
	2226	+ }
	2227	+ } else {
	2228	+ if (signal != SIGNAL_TYPE_VIRTUAL)
	2229	+ link->link_enc->funcs->disable_output(link->link_enc, signal);
	2230	+ }
	2231	+
	2232	+ if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
	2233	+ /* MST disable link only when no stream use the link */
	2234	+ if (link->mst_stream_alloc_table.stream_count <= 0)
	2235	+ link->link_status.link_active = false;
	2236	+ } else {
	2237	+ link->link_status.link_active = false;
	2238	+ }
	2239	+}
	2240	+
1832	2241	static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1833	2242	{
1834	2243	struct dc_stream_state *stream = pipe_ctx->stream;
1835		- struct dc_link *link = stream->sink->link;
	2244	+ struct dc_link *link = stream->link;
1836	2245	enum dc_color_depth display_color_depth;
1837	2246	enum engine_id eng_id;
1838	2247	struct ext_hdmi_settings settings = {0};
..	..	@@ -1841,12 +2250,12 @@
1841	2250	&& (stream->timing.v_addressable == 480);
1842	2251
1843	2252	if (stream->phy_pix_clk == 0)
1844		- stream->phy_pix_clk = stream->timing.pix_clk_khz;
	2253	+ stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
1845	2254	if (stream->phy_pix_clk > 340000)
1846	2255	is_over_340mhz = true;
1847	2256
1848	2257	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1849		- unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
	2258	+ unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
1850	2259	EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1851	2260	if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1852	2261	/* DP159, Retimer settings */
..	..	@@ -1867,11 +2276,11 @@
1867	2276
1868	2277	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1869	2278	dal_ddc_service_write_scdc_data(
1870		- stream->sink->link->ddc,
	2279	+ stream->link->ddc,
1871	2280	stream->phy_pix_clk,
1872	2281	stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1873	2282
1874		- memset(&stream->sink->link->cur_link_settings, 0,
	2283	+ memset(&stream->link->cur_link_settings, 0,
1875	2284	sizeof(struct dc_link_settings));
1876	2285
1877	2286	display_color_depth = stream->timing.display_color_depth;
..	..	@@ -1885,8 +2294,26 @@
1885	2294	pipe_ctx->stream->signal,
1886	2295	stream->phy_pix_clk);
1887	2296
1888		- if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
	2297	+ if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1889	2298	dal_ddc_service_read_scdc_data(link->ddc);
	2299	+}
	2300	+
	2301	+static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
	2302	+{
	2303	+ struct dc_stream_state *stream = pipe_ctx->stream;
	2304	+ struct dc_link *link = stream->link;
	2305	+
	2306	+ if (stream->phy_pix_clk == 0)
	2307	+ stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
	2308	+
	2309	+ memset(&stream->link->cur_link_settings, 0,
	2310	+ sizeof(struct dc_link_settings));
	2311	+
	2312	+ link->link_enc->funcs->enable_lvds_output(
	2313	+ link->link_enc,
	2314	+ pipe_ctx->clock_source->id,
	2315	+ stream->phy_pix_clk);
	2316	+
1890	2317	}
1891	2318
1892	2319	/**************************enable_link*********************************/
..	..	@@ -1895,6 +2322,19 @@
1895	2322	struct pipe_ctx *pipe_ctx)
1896	2323	{
1897	2324	enum dc_status status = DC_ERROR_UNEXPECTED;
	2325	+ struct dc_stream_state *stream = pipe_ctx->stream;
	2326	+ struct dc_link *link = stream->link;
	2327	+
	2328	+ /* There's some scenarios where driver is unloaded with display
	2329	+ * still enabled. When driver is reloaded, it may cause a display
	2330	+ * to not light up if there is a mismatch between old and new
	2331	+ * link settings. Need to call disable first before enabling at
	2332	+ * new link settings.
	2333	+ */
	2334	+ if (link->link_status.link_active) {
	2335	+ disable_link(link, pipe_ctx->stream->signal);
	2336	+ }
	2337	+
1898	2338	switch (pipe_ctx->stream->signal) {
1899	2339	case SIGNAL_TYPE_DISPLAY_PORT:
1900	2340	status = enable_link_dp(state, pipe_ctx);
..	..	@@ -1912,6 +2352,10 @@
1912	2352	enable_link_hdmi(pipe_ctx);
1913	2353	status = DC_OK;
1914	2354	break;
	2355	+ case SIGNAL_TYPE_LVDS:
	2356	+ enable_link_lvds(pipe_ctx);
	2357	+ status = DC_OK;
	2358	+ break;
1915	2359	case SIGNAL_TYPE_VIRTUAL:
1916	2360	status = DC_OK;
1917	2361	break;
..	..	@@ -1919,36 +2363,34 @@
1919	2363	break;
1920	2364	}
1921	2365
	2366	+ if (status == DC_OK)
	2367	+ pipe_ctx->stream->link->link_status.link_active = true;
	2368	+
1922	2369	return status;
1923	2370	}
1924	2371
1925		-static void disable_link(struct dc_link *link, enum signal_type signal)
	2372	+static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
1926	2373	{
1927		- /*
1928		- * TODO: implement call for dp_set_hw_test_pattern
1929		- * it is needed for compliance testing
1930		- */
1931	2374
1932		- /* here we need to specify that encoder output settings
1933		- * need to be calculated as for the set mode,
1934		- * it will lead to querying dynamic link capabilities
1935		- * which should be done before enable output */
	2375	+ uint32_t pxl_clk = timing->pix_clk_100hz;
1936	2376
1937		- if (dc_is_dp_signal(signal)) {
1938		- /* SST DP, eDP */
1939		- if (dc_is_dp_sst_signal(signal))
1940		- dp_disable_link_phy(link, signal);
1941		- else
1942		- dp_disable_link_phy_mst(link, signal);
1943		- } else
1944		- link->link_enc->funcs->disable_output(link->link_enc, signal);
	2377	+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
	2378	+ pxl_clk /= 2;
	2379	+ else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
	2380	+ pxl_clk = pxl_clk * 2 / 3;
	2381	+
	2382	+ if (timing->display_color_depth == COLOR_DEPTH_101010)
	2383	+ pxl_clk = pxl_clk * 10 / 8;
	2384	+ else if (timing->display_color_depth == COLOR_DEPTH_121212)
	2385	+ pxl_clk = pxl_clk * 12 / 8;
	2386	+
	2387	+ return pxl_clk;
1945	2388	}
1946	2389
1947	2390	static bool dp_active_dongle_validate_timing(
1948	2391	const struct dc_crtc_timing *timing,
1949	2392	const struct dpcd_caps *dpcd_caps)
1950	2393	{
1951		- unsigned int required_pix_clk = timing->pix_clk_khz;
1952	2394	const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
1953	2395
1954	2396	switch (dpcd_caps->dongle_type) {
..	..	@@ -1985,13 +2427,6 @@
1985	2427	return false;
1986	2428	}
1987	2429
1988		-
1989		- /* Check Color Depth and Pixel Clock */
1990		- if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1991		- required_pix_clk /= 2;
1992		- else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1993		- required_pix_clk = required_pix_clk * 2 / 3;
1994		-
1995	2430	switch (timing->display_color_depth) {
1996	2431	case COLOR_DEPTH_666:
1997	2432	case COLOR_DEPTH_888:
..	..	@@ -2000,14 +2435,11 @@
2000	2435	case COLOR_DEPTH_101010:
2001	2436	if (dongle_caps->dp_hdmi_max_bpc < 10)
2002	2437	return false;
2003		- required_pix_clk = required_pix_clk * 10 / 8;
2004	2438	break;
2005	2439	case COLOR_DEPTH_121212:
2006	2440	if (dongle_caps->dp_hdmi_max_bpc < 12)
2007	2441	return false;
2008		- required_pix_clk = required_pix_clk * 12 / 8;
2009	2442	break;
2010		-
2011	2443	case COLOR_DEPTH_141414:
2012	2444	case COLOR_DEPTH_161616:
2013	2445	default:
..	..	@@ -2015,7 +2447,7 @@
2015	2447	return false;
2016	2448	}
2017	2449
2018		- if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
	2450	+ if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2019	2451	return false;
2020	2452
2021	2453	return true;
..	..	@@ -2026,7 +2458,7 @@
2026	2458	struct dc_link *link,
2027	2459	const struct dc_crtc_timing *timing)
2028	2460	{
2029		- uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
	2461	+ uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2030	2462	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2031	2463
2032	2464	/* A hack to avoid failing any modes for EDID override feature on
..	..	@@ -2036,7 +2468,7 @@
2036	2468	return DC_OK;
2037	2469
2038	2470	/* Passive Dongle */
2039		- if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
	2471	+ if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2040	2472	return DC_EXCEED_DONGLE_CAP;
2041	2473
2042	2474	/* Active Dongle*/
..	..	@@ -2059,91 +2491,308 @@
2059	2491	return DC_OK;
2060	2492	}
2061	2493
	2494	+static struct abm get_abm_from_stream_res(const struct dc_link link)
	2495	+{
	2496	+ int i;
	2497	+ struct dc *dc = NULL;
	2498	+ struct abm *abm = NULL;
	2499	+
	2500	+ if (!link \|\| !link->ctx)
	2501	+ return NULL;
	2502	+
	2503	+ dc = link->ctx->dc;
	2504	+
	2505	+ for (i = 0; i < MAX_PIPES; i++) {
	2506	+ struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
	2507	+ struct dc_stream_state *stream = pipe_ctx.stream;
	2508	+
	2509	+ if (stream && stream->link == link) {
	2510	+ abm = pipe_ctx.stream_res.abm;
	2511	+ break;
	2512	+ }
	2513	+ }
	2514	+ return abm;
	2515	+}
	2516	+
2062	2517	int dc_link_get_backlight_level(const struct dc_link *link)
2063	2518	{
2064		- struct abm *abm = link->ctx->dc->res_pool->abm;
2065	2519
2066		- if (abm == NULL \|\| abm->funcs->get_current_backlight_8_bit == NULL)
	2520	+ struct abm *abm = get_abm_from_stream_res(link);
	2521	+
	2522	+ if (abm == NULL \|\| abm->funcs->get_current_backlight == NULL)
2067	2523	return DC_ERROR_UNEXPECTED;
2068	2524
2069		- return (int) abm->funcs->get_current_backlight_8_bit(abm);
	2525	+ return (int) abm->funcs->get_current_backlight(abm);
2070	2526	}
2071	2527
2072		-bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
2073		- uint32_t frame_ramp, const struct dc_stream_state *stream)
	2528	+int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2074	2529	{
2075		- struct dc *core_dc = link->ctx->dc;
2076		- struct abm *abm = core_dc->res_pool->abm;
2077		- struct dmcu *dmcu = core_dc->res_pool->dmcu;
2078		- unsigned int controller_id = 0;
2079		- bool use_smooth_brightness = true;
	2530	+ struct abm *abm = get_abm_from_stream_res(link);
	2531	+
	2532	+ if (abm == NULL \|\| abm->funcs->get_target_backlight == NULL)
	2533	+ return DC_ERROR_UNEXPECTED;
	2534	+
	2535	+ return (int) abm->funcs->get_target_backlight(abm);
	2536	+}
	2537	+
	2538	+static struct pipe_ctx get_pipe_from_link(const struct dc_link link)
	2539	+{
2080	2540	int i;
2081		- DC_LOGGER_INIT(link->ctx->logger);
	2541	+ struct dc *dc = link->ctx->dc;
	2542	+ struct pipe_ctx *pipe_ctx = NULL;
2082	2543
2083		- if ((dmcu == NULL) \|\|
2084		- (abm == NULL) \|\|
2085		- (abm->funcs->set_backlight_level == NULL))
2086		- return false;
2087		-
2088		- if (stream) {
2089		- if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
2090		- frame_ramp = 0;
2091		-
2092		- ((struct dc_stream_state *)stream)->bl_pwm_level = level;
2093		- }
2094		-
2095		- use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2096		-
2097		- DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", level, level);
2098		-
2099		- if (dc_is_embedded_signal(link->connector_signal)) {
2100		- if (stream != NULL) {
2101		- for (i = 0; i < MAX_PIPES; i++) {
2102		- if (core_dc->current_state->res_ctx.
2103		- pipe_ctx[i].stream
2104		- == stream)
2105		- /* DMCU -1 for all controller id values,
2106		- * therefore +1 here
2107		- */
2108		- controller_id =
2109		- core_dc->current_state->
2110		- res_ctx.pipe_ctx[i].stream_res.tg->inst +
2111		- 1;
	2544	+ for (i = 0; i < MAX_PIPES; i++) {
	2545	+ if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
	2546	+ if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
	2547	+ pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
	2548	+ break;
2112	2549	}
2113	2550	}
2114		- abm->funcs->set_backlight_level(
2115		- abm,
2116		- level,
2117		- frame_ramp,
2118		- controller_id,
2119		- use_smooth_brightness);
2120	2551	}
2121	2552
	2553	+ return pipe_ctx;
	2554	+}
	2555	+
	2556	+bool dc_link_set_backlight_level(const struct dc_link *link,
	2557	+ uint32_t backlight_pwm_u16_16,
	2558	+ uint32_t frame_ramp)
	2559	+{
	2560	+ struct dc *dc = link->ctx->dc;
	2561	+
	2562	+ DC_LOGGER_INIT(link->ctx->logger);
	2563	+ DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
	2564	+ backlight_pwm_u16_16, backlight_pwm_u16_16);
	2565	+
	2566	+ if (dc_is_embedded_signal(link->connector_signal)) {
	2567	+ struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
	2568	+
	2569	+ if (pipe_ctx) {
	2570	+ /* Disable brightness ramping when the display is blanked
	2571	+ * as it can hang the DMCU
	2572	+ */
	2573	+ if (pipe_ctx->plane_state == NULL)
	2574	+ frame_ramp = 0;
	2575	+ } else {
	2576	+ return false;
	2577	+ }
	2578	+
	2579	+ dc->hwss.set_backlight_level(
	2580	+ pipe_ctx,
	2581	+ backlight_pwm_u16_16,
	2582	+ frame_ramp);
	2583	+ }
2122	2584	return true;
2123	2585	}
2124	2586
2125		-bool dc_link_set_abm_disable(const struct dc_link *link)
	2587	+bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
2126	2588	{
2127		- struct dc *core_dc = link->ctx->dc;
2128		- struct abm *abm = core_dc->res_pool->abm;
	2589	+ struct dc *dc = link->ctx->dc;
	2590	+ struct dmcu *dmcu = dc->res_pool->dmcu;
	2591	+ struct dmub_psr *psr = dc->res_pool->psr;
2129	2592
2130		- if ((abm == NULL) \|\| (abm->funcs->set_backlight_level == NULL))
	2593	+ link->psr_settings.psr_allow_active = allow_active;
	2594	+
	2595	+ if (psr != NULL && link->psr_settings.psr_feature_enabled)
	2596	+ psr->funcs->psr_enable(psr, allow_active, wait);
	2597	+ else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
	2598	+ dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
	2599	+ else
2131	2600	return false;
2132	2601
2133		- abm->funcs->set_abm_immediate_disable(abm);
	2602	+ return true;
	2603	+}
	2604	+
	2605	+bool dc_link_get_psr_state(const struct dc_link link, uint32_t psr_state)
	2606	+{
	2607	+ struct dc *dc = link->ctx->dc;
	2608	+ struct dmcu *dmcu = dc->res_pool->dmcu;
	2609	+ struct dmub_psr *psr = dc->res_pool->psr;
	2610	+
	2611	+ if (psr != NULL && link->psr_settings.psr_feature_enabled)
	2612	+ psr->funcs->psr_get_state(psr, psr_state);
	2613	+ else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
	2614	+ dmcu->funcs->get_psr_state(dmcu, psr_state);
2134	2615
2135	2616	return true;
2136	2617	}
2137	2618
2138		-bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
	2619	+static inline enum physical_phy_id
	2620	+transmitter_to_phy_id(enum transmitter transmitter_value)
2139	2621	{
2140		- struct dc *core_dc = link->ctx->dc;
2141		- struct dmcu *dmcu = core_dc->res_pool->dmcu;
	2622	+ switch (transmitter_value) {
	2623	+ case TRANSMITTER_UNIPHY_A:
	2624	+ return PHYLD_0;
	2625	+ case TRANSMITTER_UNIPHY_B:
	2626	+ return PHYLD_1;
	2627	+ case TRANSMITTER_UNIPHY_C:
	2628	+ return PHYLD_2;
	2629	+ case TRANSMITTER_UNIPHY_D:
	2630	+ return PHYLD_3;
	2631	+ case TRANSMITTER_UNIPHY_E:
	2632	+ return PHYLD_4;
	2633	+ case TRANSMITTER_UNIPHY_F:
	2634	+ return PHYLD_5;
	2635	+ case TRANSMITTER_NUTMEG_CRT:
	2636	+ return PHYLD_6;
	2637	+ case TRANSMITTER_TRAVIS_CRT:
	2638	+ return PHYLD_7;
	2639	+ case TRANSMITTER_TRAVIS_LCD:
	2640	+ return PHYLD_8;
	2641	+ case TRANSMITTER_UNIPHY_G:
	2642	+ return PHYLD_9;
	2643	+ case TRANSMITTER_COUNT:
	2644	+ return PHYLD_COUNT;
	2645	+ case TRANSMITTER_UNKNOWN:
	2646	+ return PHYLD_UNKNOWN;
	2647	+ default:
	2648	+ WARN_ONCE(1, "Unknown transmitter value %d\n",
	2649	+ transmitter_value);
	2650	+ return PHYLD_UNKNOWN;
	2651	+ }
	2652	+}
2142	2653
2143		- if (dmcu != NULL && link->psr_enabled)
2144		- dmcu->funcs->set_psr_enable(dmcu, enable, wait);
	2654	+bool dc_link_setup_psr(struct dc_link *link,
	2655	+ const struct dc_stream_state stream, struct psr_config psr_config,
	2656	+ struct psr_context *psr_context)
	2657	+{
	2658	+ struct dc *dc;
	2659	+ struct dmcu *dmcu;
	2660	+ struct dmub_psr *psr;
	2661	+ int i;
	2662	+ /* updateSinkPsrDpcdConfig*/
	2663	+ union dpcd_psr_configuration psr_configuration;
	2664	+
	2665	+ psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
	2666	+
	2667	+ if (!link)
	2668	+ return false;
	2669	+
	2670	+ dc = link->ctx->dc;
	2671	+ dmcu = dc->res_pool->dmcu;
	2672	+ psr = dc->res_pool->psr;
	2673	+
	2674	+ if (!dmcu && !psr)
	2675	+ return false;
	2676	+
	2677	+
	2678	+ memset(&psr_configuration, 0, sizeof(psr_configuration));
	2679	+
	2680	+ psr_configuration.bits.ENABLE = 1;
	2681	+ psr_configuration.bits.CRC_VERIFICATION = 1;
	2682	+ psr_configuration.bits.FRAME_CAPTURE_INDICATION =
	2683	+ psr_config->psr_frame_capture_indication_req;
	2684	+
	2685	+ /* Check for PSR v2*/
	2686	+ if (psr_config->psr_version == 0x2) {
	2687	+ /* For PSR v2 selective update.
	2688	+ * Indicates whether sink should start capturing
	2689	+ * immediately following active scan line,
	2690	+ * or starting with the 2nd active scan line.
	2691	+ */
	2692	+ psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
	2693	+ /*For PSR v2, determines whether Sink should generate
	2694	+ * IRQ_HPD when CRC mismatch is detected.
	2695	+ */
	2696	+ psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
	2697	+ }
	2698	+
	2699	+ dm_helpers_dp_write_dpcd(
	2700	+ link->ctx,
	2701	+ link,
	2702	+ 368,
	2703	+ &psr_configuration.raw,
	2704	+ sizeof(psr_configuration.raw));
	2705	+
	2706	+ psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
	2707	+ psr_context->transmitterId = link->link_enc->transmitter;
	2708	+ psr_context->engineId = link->link_enc->preferred_engine;
	2709	+
	2710	+ for (i = 0; i < MAX_PIPES; i++) {
	2711	+ if (dc->current_state->res_ctx.pipe_ctx[i].stream
	2712	+ == stream) {
	2713	+ /* dmcu -1 for all controller id values,
	2714	+ * therefore +1 here
	2715	+ */
	2716	+ psr_context->controllerId =
	2717	+ dc->current_state->res_ctx.
	2718	+ pipe_ctx[i].stream_res.tg->inst + 1;
	2719	+ break;
	2720	+ }
	2721	+ }
	2722	+
	2723	+ /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
	2724	+ psr_context->phyType = PHY_TYPE_UNIPHY;
	2725	+ /PhyId is associated with the transmitter id/
	2726	+ psr_context->smuPhyId =
	2727	+ transmitter_to_phy_id(link->link_enc->transmitter);
	2728	+
	2729	+ psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
	2730	+ psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
	2731	+ timing.pix_clk_100hz * 100),
	2732	+ stream->timing.v_total),
	2733	+ stream->timing.h_total);
	2734	+
	2735	+ psr_context->psrSupportedDisplayConfig = true;
	2736	+ psr_context->psrExitLinkTrainingRequired =
	2737	+ psr_config->psr_exit_link_training_required;
	2738	+ psr_context->sdpTransmitLineNumDeadline =
	2739	+ psr_config->psr_sdp_transmit_line_num_deadline;
	2740	+ psr_context->psrFrameCaptureIndicationReq =
	2741	+ psr_config->psr_frame_capture_indication_req;
	2742	+
	2743	+ psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
	2744	+
	2745	+ psr_context->numberOfControllers =
	2746	+ link->dc->res_pool->timing_generator_count;
	2747	+
	2748	+ psr_context->rfb_update_auto_en = true;
	2749	+
	2750	+ /* 2 frames before enter PSR. */
	2751	+ psr_context->timehyst_frames = 2;
	2752	+ /* half a frame
	2753	+ * (units in 100 lines, i.e. a value of 1 represents 100 lines)
	2754	+ */
	2755	+ psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
	2756	+ psr_context->aux_repeats = 10;
	2757	+
	2758	+ psr_context->psr_level.u32all = 0;
	2759	+
	2760	+#if defined(CONFIG_DRM_AMD_DC_DCN)
	2761	+ /skip power down the single pipe since it blocks the cstate/
	2762	+ if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
	2763	+ psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
	2764	+#endif
	2765	+
	2766	+ /* SMU will perform additional powerdown sequence.
	2767	+ * For unsupported ASICs, set psr_level flag to skip PSR
	2768	+ * static screen notification to SMU.
	2769	+ * (Always set for DAL2, did not check ASIC)
	2770	+ */
	2771	+ psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
	2772	+
	2773	+ /* Complete PSR entry before aborting to prevent intermittent
	2774	+ * freezes on certain eDPs
	2775	+ */
	2776	+ psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
	2777	+
	2778	+ /* Controls additional delay after remote frame capture before
	2779	+ * continuing power down, default = 0
	2780	+ */
	2781	+ psr_context->frame_delay = 0;
	2782	+
	2783	+ if (psr)
	2784	+ link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
	2785	+ else
	2786	+ link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
	2787	+
	2788	+ /* psr_enabled == 0 indicates setup_psr did not succeed, but this
	2789	+ * should not happen since firmware should be running at this point
	2790	+ */
	2791	+ if (link->psr_settings.psr_feature_enabled == 0)
	2792	+ ASSERT(0);
2145	2793
2146	2794	return true;
	2795	+
2147	2796	}
2148	2797
2149	2798	const struct dc_link_status dc_link_get_status(const struct dc_link link)
..	..	@@ -2159,39 +2808,24 @@
2159	2808
2160	2809	static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2161	2810	{
2162		- struct dc_link_settings *link_settings =
2163		- &stream->sink->link->cur_link_settings;
2164		- uint32_t link_rate_in_mbps =
2165		- link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2166		- struct fixed31_32 mbps = dc_fixpt_from_int(
2167		- link_rate_in_mbps * link_settings->lane_count);
	2811	+ struct fixed31_32 mbytes_per_sec;
	2812	+ uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
	2813	+ &stream->link->cur_link_settings);
	2814	+ link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2168	2815
2169		- return dc_fixpt_div_int(mbps, 54);
2170		-}
	2816	+ mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2171	2817
2172		-static int get_color_depth(enum dc_color_depth color_depth)
2173		-{
2174		- switch (color_depth) {
2175		- case COLOR_DEPTH_666: return 6;
2176		- case COLOR_DEPTH_888: return 8;
2177		- case COLOR_DEPTH_101010: return 10;
2178		- case COLOR_DEPTH_121212: return 12;
2179		- case COLOR_DEPTH_141414: return 14;
2180		- case COLOR_DEPTH_161616: return 16;
2181		- default: return 0;
2182		- }
	2818	+ return dc_fixpt_div_int(mbytes_per_sec, 54);
2183	2819	}
2184	2820
2185	2821	static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2186	2822	{
2187		- uint32_t bpc;
2188	2823	uint64_t kbps;
2189	2824	struct fixed31_32 peak_kbps;
2190	2825	uint32_t numerator;
2191	2826	uint32_t denominator;
2192	2827
2193		- bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2194		- kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
	2828	+ kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2195	2829
2196	2830	/*
2197	2831	* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
..	..	@@ -2264,10 +2898,10 @@
2264	2898	/* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2265	2899	* because stream_encoder is not exposed to dm
2266	2900	*/
2267		-static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
	2901	+enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2268	2902	{
2269	2903	struct dc_stream_state *stream = pipe_ctx->stream;
2270		- struct dc_link *link = stream->sink->link;
	2904	+ struct dc_link *link = stream->link;
2271	2905	struct link_encoder *link_encoder = link->link_enc;
2272	2906	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2273	2907	struct dp_mst_stream_allocation_table proposed_table = {0};
..	..	@@ -2275,6 +2909,7 @@
2275	2909	struct fixed31_32 pbn;
2276	2910	struct fixed31_32 pbn_per_slot;
2277	2911	uint8_t i;
	2912	+ enum act_return_status ret;
2278	2913	DC_LOGGER_INIT(link->ctx->logger);
2279	2914
2280	2915	/* enable_link_dp_mst already check link->enabled_stream_count
..	..	@@ -2322,21 +2957,23 @@
2322	2957	&link->mst_stream_alloc_table);
2323	2958
2324	2959	/* send down message */
2325		- dm_helpers_dp_mst_poll_for_allocation_change_trigger(
	2960	+ ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2326	2961	stream->ctx,
2327	2962	stream);
2328	2963
2329		- dm_helpers_dp_mst_send_payload_allocation(
2330		- stream->ctx,
2331		- stream,
2332		- true);
	2964	+ if (ret != ACT_LINK_LOST) {
	2965	+ dm_helpers_dp_mst_send_payload_allocation(
	2966	+ stream->ctx,
	2967	+ stream,
	2968	+ true);
	2969	+ }
2333	2970
2334	2971	/* slot X.Y for only current stream */
2335	2972	pbn_per_slot = get_pbn_per_slot(stream);
2336	2973	pbn = get_pbn_from_timing(pipe_ctx);
2337	2974	avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2338	2975
2339		- stream_encoder->funcs->set_mst_bandwidth(
	2976	+ stream_encoder->funcs->set_throttled_vcp_size(
2340	2977	stream_encoder,
2341	2978	avg_time_slots_per_mtp);
2342	2979
..	..	@@ -2347,7 +2984,7 @@
2347	2984	static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2348	2985	{
2349	2986	struct dc_stream_state *stream = pipe_ctx->stream;
2350		- struct dc_link *link = stream->sink->link;
	2987	+ struct dc_link *link = stream->link;
2351	2988	struct link_encoder *link_encoder = link->link_enc;
2352	2989	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2353	2990	struct dp_mst_stream_allocation_table proposed_table = {0};
..	..	@@ -2364,7 +3001,7 @@
2364	3001	*/
2365	3002
2366	3003	/* slot X.Y */
2367		- stream_encoder->funcs->set_mst_bandwidth(
	3004	+ stream_encoder->funcs->set_throttled_vcp_size(
2368	3005	stream_encoder,
2369	3006	avg_time_slots_per_mtp);
2370	3007
..	..	@@ -2422,30 +3059,181 @@
2422	3059	return DC_OK;
2423	3060	}
2424	3061
	3062	+enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link)
	3063	+{
	3064	+ int i;
	3065	+ struct pipe_ctx *pipe_ctx;
	3066	+
	3067	+ // Clear all of MST payload then reallocate
	3068	+ for (i = 0; i < MAX_PIPES; i++) {
	3069	+ pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
	3070	+
	3071	+ /* driver enable split pipe for external monitors
	3072	+ * we have to check pipe_ctx is split pipe or not
	3073	+ * If it's split pipe, driver using top pipe to
	3074	+ * reaallocate.
	3075	+ */
	3076	+ if (!pipe_ctx \|\| pipe_ctx->top_pipe)
	3077	+ continue;
	3078	+
	3079	+ if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
	3080	+ pipe_ctx->stream->dpms_off == false &&
	3081	+ pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
	3082	+ deallocate_mst_payload(pipe_ctx);
	3083	+ }
	3084	+ }
	3085	+
	3086	+ for (i = 0; i < MAX_PIPES; i++) {
	3087	+ pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
	3088	+
	3089	+ if (!pipe_ctx \|\| pipe_ctx->top_pipe)
	3090	+ continue;
	3091	+
	3092	+ if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
	3093	+ pipe_ctx->stream->dpms_off == false &&
	3094	+ pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
	3095	+ /* enable/disable PHY will clear connection between BE and FE
	3096	+ * need to restore it.
	3097	+ */
	3098	+ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
	3099	+ pipe_ctx->stream_res.stream_enc->id, true);
	3100	+ dc_link_allocate_mst_payload(pipe_ctx);
	3101	+ }
	3102	+ }
	3103	+
	3104	+ return DC_OK;
	3105	+}
	3106	+
	3107	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	3108	+static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
	3109	+{
	3110	+ struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
	3111	+ if (cp_psp && cp_psp->funcs.update_stream_config) {
	3112	+ struct cp_psp_stream_config config;
	3113	+
	3114	+ memset(&config, 0, sizeof(config));
	3115	+
	3116	+ config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
	3117	+ /stream_enc_inst/
	3118	+ config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
	3119	+ config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
	3120	+ config.dpms_off = dpms_off;
	3121	+ config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
	3122	+ config.mst_supported = (pipe_ctx->stream->signal ==
	3123	+ SIGNAL_TYPE_DISPLAY_PORT_MST);
	3124	+ cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
	3125	+ }
	3126	+}
	3127	+#endif
	3128	+
2425	3129	void core_link_enable_stream(
2426	3130	struct dc_state *state,
2427	3131	struct pipe_ctx *pipe_ctx)
2428	3132	{
2429		- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
	3133	+ struct dc *dc = pipe_ctx->stream->ctx->dc;
	3134	+ struct dc_stream_state *stream = pipe_ctx->stream;
2430	3135	enum dc_status status;
	3136	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	3137	+ enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
	3138	+#endif
2431	3139	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2432	3140
2433		- /* eDP lit up by bios already, no need to enable again. */
2434		- if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2435		- core_dc->apply_edp_fast_boot_optimization) {
2436		- core_dc->apply_edp_fast_boot_optimization = false;
2437		- pipe_ctx->stream->dpms_off = false;
	3141	+ if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
	3142	+ dc_is_virtual_signal(pipe_ctx->stream->signal))
2438	3143	return;
	3144	+
	3145	+ if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
	3146	+ stream->link->link_enc->funcs->setup(
	3147	+ stream->link->link_enc,
	3148	+ pipe_ctx->stream->signal);
	3149	+ pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
	3150	+ pipe_ctx->stream_res.stream_enc,
	3151	+ pipe_ctx->stream_res.tg->inst,
	3152	+ stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2439	3153	}
2440	3154
2441		- if (pipe_ctx->stream->dpms_off)
2442		- return;
	3155	+ if (dc_is_dp_signal(pipe_ctx->stream->signal))
	3156	+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
	3157	+ pipe_ctx->stream_res.stream_enc,
	3158	+ &stream->timing,
	3159	+ stream->output_color_space,
	3160	+ stream->use_vsc_sdp_for_colorimetry,
	3161	+ stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
2443	3162
2444		- status = enable_link(state, pipe_ctx);
	3163	+ if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
	3164	+ pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
	3165	+ pipe_ctx->stream_res.stream_enc,
	3166	+ &stream->timing,
	3167	+ stream->phy_pix_clk,
	3168	+ pipe_ctx->stream_res.audio != NULL);
2445	3169
2446		- if (status != DC_OK) {
	3170	+ pipe_ctx->stream->link->link_state_valid = true;
	3171	+
	3172	+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	3173	+ if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
	3174	+ pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
	3175	+#endif
	3176	+
	3177	+ if (dc_is_dvi_signal(pipe_ctx->stream->signal))
	3178	+ pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
	3179	+ pipe_ctx->stream_res.stream_enc,
	3180	+ &stream->timing,
	3181	+ (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
	3182	+ true : false);
	3183	+
	3184	+ if (dc_is_lvds_signal(pipe_ctx->stream->signal))
	3185	+ pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
	3186	+ pipe_ctx->stream_res.stream_enc,
	3187	+ &stream->timing);
	3188	+
	3189	+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
	3190	+ bool apply_edp_fast_boot_optimization =
	3191	+ pipe_ctx->stream->apply_edp_fast_boot_optimization;
	3192	+
	3193	+ pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
	3194	+
	3195	+ resource_build_info_frame(pipe_ctx);
	3196	+ dc->hwss.update_info_frame(pipe_ctx);
	3197	+
	3198	+ /* Do not touch link on seamless boot optimization. */
	3199	+ if (pipe_ctx->stream->apply_seamless_boot_optimization) {
	3200	+ pipe_ctx->stream->dpms_off = false;
	3201	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	3202	+ update_psp_stream_config(pipe_ctx, false);
	3203	+#endif
	3204	+ return;
	3205	+ }
	3206	+
	3207	+ /* eDP lit up by bios already, no need to enable again. */
	3208	+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
	3209	+ apply_edp_fast_boot_optimization) {
	3210	+ pipe_ctx->stream->dpms_off = false;
	3211	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	3212	+ update_psp_stream_config(pipe_ctx, false);
	3213	+#endif
	3214	+ return;
	3215	+ }
	3216	+
	3217	+ if (pipe_ctx->stream->dpms_off)
	3218	+ return;
	3219	+
	3220	+ /* Have to setup DSC before DIG FE and BE are connected (which happens before the
	3221	+ * link training). This is to make sure the bandwidth sent to DIG BE won't be
	3222	+ * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
	3223	+ * will be automatically set at a later time when the video is enabled
	3224	+ * (DP_VID_STREAM_EN = 1).
	3225	+ */
	3226	+ if (pipe_ctx->stream->timing.flags.DSC) {
	3227	+ if (dc_is_dp_signal(pipe_ctx->stream->signal) \|\|
	3228	+ dc_is_virtual_signal(pipe_ctx->stream->signal))
	3229	+ dp_set_dsc_enable(pipe_ctx, true);
	3230	+ }
	3231	+
	3232	+ status = enable_link(state, pipe_ctx);
	3233	+
	3234	+ if (status != DC_OK) {
2447	3235	DC_LOG_WARNING("enabling link %u failed: %d\n",
2448		- pipe_ctx->stream->sink->link->link_index,
	3236	+ pipe_ctx->stream->link->link_index,
2449	3237	status);
2450	3238
2451	3239	/* Abort stream enable unless the failure was due to
..	..	@@ -2458,47 +3246,125 @@
2458	3246	BREAK_TO_DEBUGGER();
2459	3247	return;
2460	3248	}
	3249	+ }
	3250	+
	3251	+ dc->hwss.enable_audio_stream(pipe_ctx);
	3252	+
	3253	+ /* turn off otg test pattern if enable */
	3254	+ if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
	3255	+ pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
	3256	+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
	3257	+ COLOR_DEPTH_UNDEFINED);
	3258	+
	3259	+ /* This second call is needed to reconfigure the DIG
	3260	+ * as a workaround for the incorrect value being applied
	3261	+ * from transmitter control.
	3262	+ */
	3263	+ if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
	3264	+ stream->link->link_enc->funcs->setup(
	3265	+ stream->link->link_enc,
	3266	+ pipe_ctx->stream->signal);
	3267	+
	3268	+ dc->hwss.enable_stream(pipe_ctx);
	3269	+
	3270	+ /* Set DPS PPS SDP (AKA "info frames") */
	3271	+ if (pipe_ctx->stream->timing.flags.DSC) {
	3272	+ if (dc_is_dp_signal(pipe_ctx->stream->signal) \|\|
	3273	+ dc_is_virtual_signal(pipe_ctx->stream->signal))
	3274	+ dp_set_dsc_pps_sdp(pipe_ctx, true);
	3275	+ }
	3276	+
	3277	+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
	3278	+ dc_link_allocate_mst_payload(pipe_ctx);
	3279	+
	3280	+ dc->hwss.unblank_stream(pipe_ctx,
	3281	+ &pipe_ctx->stream->link->cur_link_settings);
	3282	+
	3283	+ if (stream->sink_patches.delay_ignore_msa > 0)
	3284	+ msleep(stream->sink_patches.delay_ignore_msa);
	3285	+
	3286	+ if (dc_is_dp_signal(pipe_ctx->stream->signal))
	3287	+ enable_stream_features(pipe_ctx);
	3288	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	3289	+ update_psp_stream_config(pipe_ctx, false);
	3290	+#endif
	3291	+ } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
	3292	+ if (dc_is_dp_signal(pipe_ctx->stream->signal) \|\|
	3293	+ dc_is_virtual_signal(pipe_ctx->stream->signal))
	3294	+ dp_set_dsc_enable(pipe_ctx, true);
	3295	+
2461	3296	}
2462	3297
2463		- core_dc->hwss.enable_audio_stream(pipe_ctx);
2464		-
2465		- /* turn off otg test pattern if enable */
2466		- if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2467		- pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2468		- CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2469		- COLOR_DEPTH_UNDEFINED);
2470		-
2471		- core_dc->hwss.enable_stream(pipe_ctx);
2472		-
2473		- if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2474		- allocate_mst_payload(pipe_ctx);
2475		-
2476		- core_dc->hwss.unblank_stream(pipe_ctx,
2477		- &pipe_ctx->stream->sink->link->cur_link_settings);
	3298	+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
	3299	+ core_link_set_avmute(pipe_ctx, false);
	3300	+ }
2478	3301	}
2479	3302
2480		-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
	3303	+void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
2481	3304	{
2482		- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
	3305	+ struct dc *dc = pipe_ctx->stream->ctx->dc;
	3306	+ struct dc_stream_state *stream = pipe_ctx->stream;
	3307	+ struct dc_link *link = stream->sink->link;
2483	3308
2484		- core_dc->hwss.blank_stream(pipe_ctx);
	3309	+ if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
	3310	+ dc_is_virtual_signal(pipe_ctx->stream->signal))
	3311	+ return;
	3312	+
	3313	+ if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
	3314	+ core_link_set_avmute(pipe_ctx, true);
	3315	+ }
	3316	+
	3317	+#if defined(CONFIG_DRM_AMD_DC_HDCP)
	3318	+ update_psp_stream_config(pipe_ctx, true);
	3319	+#endif
	3320	+ dc->hwss.blank_stream(pipe_ctx);
2485	3321
2486	3322	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2487	3323	deallocate_mst_payload(pipe_ctx);
2488	3324
2489		- core_dc->hwss.disable_stream(pipe_ctx, option);
	3325	+ if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
	3326	+ struct ext_hdmi_settings settings = {0};
	3327	+ enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
2490	3328
2491		- disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
	3329	+ unsigned short masked_chip_caps = link->chip_caps &
	3330	+ EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
	3331	+ //Need to inform that sink is going to use legacy HDMI mode.
	3332	+ dal_ddc_service_write_scdc_data(
	3333	+ link->ddc,
	3334	+ 165000,//vbios only handles 165Mhz.
	3335	+ false);
	3336	+ if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
	3337	+ /* DP159, Retimer settings */
	3338	+ if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
	3339	+ write_i2c_retimer_setting(pipe_ctx,
	3340	+ false, false, &settings);
	3341	+ else
	3342	+ write_i2c_default_retimer_setting(pipe_ctx,
	3343	+ false, false);
	3344	+ } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
	3345	+ /* PI3EQX1204, Redriver settings */
	3346	+ write_i2c_redriver_setting(pipe_ctx, false);
	3347	+ }
	3348	+ }
	3349	+
	3350	+ disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
	3351	+
	3352	+ dc->hwss.disable_stream(pipe_ctx);
	3353	+
	3354	+ if (pipe_ctx->stream->timing.flags.DSC) {
	3355	+ if (dc_is_dp_signal(pipe_ctx->stream->signal))
	3356	+ dp_set_dsc_enable(pipe_ctx, false);
	3357	+ }
2492	3358	}
2493	3359
2494	3360	void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2495	3361	{
2496		- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
	3362	+ struct dc *dc = pipe_ctx->stream->ctx->dc;
2497	3363
2498		- if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
	3364	+ if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
2499	3365	return;
2500	3366
2501		- core_dc->hwss.set_avmute(pipe_ctx, enable);
	3367	+ dc->hwss.set_avmute(pipe_ctx, enable);
2502	3368	}
2503	3369
2504	3370	/**
..	..	@@ -2550,3 +3416,246 @@
2550	3416	}
2551	3417	}
2552	3418
	3419	+uint32_t dc_bandwidth_in_kbps_from_timing(
	3420	+ const struct dc_crtc_timing *timing)
	3421	+{
	3422	+ uint32_t bits_per_channel = 0;
	3423	+ uint32_t kbps;
	3424	+ struct fixed31_32 link_bw_kbps;
	3425	+
	3426	+ if (timing->flags.DSC) {
	3427	+ link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz);
	3428	+ link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
	3429	+ link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, timing->dsc_cfg.bits_per_pixel);
	3430	+ kbps = dc_fixpt_ceil(link_bw_kbps);
	3431	+ return kbps;
	3432	+ }
	3433	+
	3434	+ switch (timing->display_color_depth) {
	3435	+ case COLOR_DEPTH_666:
	3436	+ bits_per_channel = 6;
	3437	+ break;
	3438	+ case COLOR_DEPTH_888:
	3439	+ bits_per_channel = 8;
	3440	+ break;
	3441	+ case COLOR_DEPTH_101010:
	3442	+ bits_per_channel = 10;
	3443	+ break;
	3444	+ case COLOR_DEPTH_121212:
	3445	+ bits_per_channel = 12;
	3446	+ break;
	3447	+ case COLOR_DEPTH_141414:
	3448	+ bits_per_channel = 14;
	3449	+ break;
	3450	+ case COLOR_DEPTH_161616:
	3451	+ bits_per_channel = 16;
	3452	+ break;
	3453	+ default:
	3454	+ break;
	3455	+ }
	3456	+
	3457	+ ASSERT(bits_per_channel != 0);
	3458	+
	3459	+ kbps = timing->pix_clk_100hz / 10;
	3460	+ kbps *= bits_per_channel;
	3461	+
	3462	+ if (timing->flags.Y_ONLY != 1) {
	3463	+ /Only YOnly make reduce bandwidth by 1/3 compares to RGB/
	3464	+ kbps *= 3;
	3465	+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
	3466	+ kbps /= 2;
	3467	+ else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
	3468	+ kbps = kbps * 2 / 3;
	3469	+ }
	3470	+
	3471	+ return kbps;
	3472	+
	3473	+}
	3474	+
	3475	+void dc_link_set_drive_settings(struct dc *dc,
	3476	+ struct link_training_settings *lt_settings,
	3477	+ const struct dc_link *link)
	3478	+{
	3479	+
	3480	+ int i;
	3481	+
	3482	+ for (i = 0; i < dc->link_count; i++) {
	3483	+ if (dc->links[i] == link)
	3484	+ break;
	3485	+ }
	3486	+
	3487	+ if (i >= dc->link_count)
	3488	+ ASSERT_CRITICAL(false);
	3489	+
	3490	+ dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
	3491	+}
	3492	+
	3493	+void dc_link_perform_link_training(struct dc *dc,
	3494	+ struct dc_link_settings *link_setting,
	3495	+ bool skip_video_pattern)
	3496	+{
	3497	+ int i;
	3498	+
	3499	+ for (i = 0; i < dc->link_count; i++)
	3500	+ dc_link_dp_perform_link_training(
	3501	+ dc->links[i],
	3502	+ link_setting,
	3503	+ skip_video_pattern);
	3504	+}
	3505	+
	3506	+void dc_link_set_preferred_link_settings(struct dc *dc,
	3507	+ struct dc_link_settings *link_setting,
	3508	+ struct dc_link *link)
	3509	+{
	3510	+ int i;
	3511	+ struct pipe_ctx *pipe;
	3512	+ struct dc_stream_state *link_stream;
	3513	+ struct dc_link_settings store_settings = *link_setting;
	3514	+
	3515	+ link->preferred_link_setting = store_settings;
	3516	+
	3517	+ /* Retrain with preferred link settings only relevant for
	3518	+ * DP signal type
	3519	+ * Check for non-DP signal or if passive dongle present
	3520	+ */
	3521	+ if (!dc_is_dp_signal(link->connector_signal) \|\|
	3522	+ link->dongle_max_pix_clk > 0)
	3523	+ return;
	3524	+
	3525	+ for (i = 0; i < MAX_PIPES; i++) {
	3526	+ pipe = &dc->current_state->res_ctx.pipe_ctx[i];
	3527	+ if (pipe->stream && pipe->stream->link) {
	3528	+ if (pipe->stream->link == link) {
	3529	+ link_stream = pipe->stream;
	3530	+ break;
	3531	+ }
	3532	+ }
	3533	+ }
	3534	+
	3535	+ /* Stream not found */
	3536	+ if (i == MAX_PIPES)
	3537	+ return;
	3538	+
	3539	+ /* Cannot retrain link if backend is off */
	3540	+ if (link_stream->dpms_off)
	3541	+ return;
	3542	+
	3543	+ decide_link_settings(link_stream, &store_settings);
	3544	+
	3545	+ if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
	3546	+ (store_settings.link_rate != LINK_RATE_UNKNOWN))
	3547	+ dp_retrain_link_dp_test(link, &store_settings, false);
	3548	+}
	3549	+
	3550	+void dc_link_set_preferred_training_settings(struct dc *dc,
	3551	+ struct dc_link_settings *link_setting,
	3552	+ struct dc_link_training_overrides *lt_overrides,
	3553	+ struct dc_link *link,
	3554	+ bool skip_immediate_retrain)
	3555	+{
	3556	+ if (lt_overrides != NULL)
	3557	+ link->preferred_training_settings = *lt_overrides;
	3558	+ else
	3559	+ memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
	3560	+
	3561	+ if (link_setting != NULL) {
	3562	+ link->preferred_link_setting = *link_setting;
	3563	+ } else {
	3564	+ link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
	3565	+ link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
	3566	+ }
	3567	+
	3568	+ /* Retrain now, or wait until next stream update to apply */
	3569	+ if (skip_immediate_retrain == false)
	3570	+ dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
	3571	+}
	3572	+
	3573	+void dc_link_enable_hpd(const struct dc_link *link)
	3574	+{
	3575	+ dc_link_dp_enable_hpd(link);
	3576	+}
	3577	+
	3578	+void dc_link_disable_hpd(const struct dc_link *link)
	3579	+{
	3580	+ dc_link_dp_disable_hpd(link);
	3581	+}
	3582	+
	3583	+void dc_link_set_test_pattern(struct dc_link *link,
	3584	+ enum dp_test_pattern test_pattern,
	3585	+ enum dp_test_pattern_color_space test_pattern_color_space,
	3586	+ const struct link_training_settings *p_link_settings,
	3587	+ const unsigned char *p_custom_pattern,
	3588	+ unsigned int cust_pattern_size)
	3589	+{
	3590	+ if (link != NULL)
	3591	+ dc_link_dp_set_test_pattern(
	3592	+ link,
	3593	+ test_pattern,
	3594	+ test_pattern_color_space,
	3595	+ p_link_settings,
	3596	+ p_custom_pattern,
	3597	+ cust_pattern_size);
	3598	+}
	3599	+
	3600	+uint32_t dc_link_bandwidth_kbps(
	3601	+ const struct dc_link *link,
	3602	+ const struct dc_link_settings *link_setting)
	3603	+{
	3604	+ uint32_t link_bw_kbps =
	3605	+ link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
	3606	+
	3607	+ link_bw_kbps = 8; / 8 bits per byte*/
	3608	+ link_bw_kbps *= link_setting->lane_count;
	3609	+
	3610	+ if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
	3611	+ /* Account for FEC overhead.
	3612	+ * We have to do it based on caps,
	3613	+ * and not based on FEC being set ready,
	3614	+ * because FEC is set ready too late in
	3615	+ * the process to correctly be picked up
	3616	+ * by mode enumeration.
	3617	+ *
	3618	+ * There's enough zeros at the end of 'kbps'
	3619	+ * that make the below operation 100% precise
	3620	+ * for our purposes.
	3621	+ * 'long long' makes it work even for HDMI 2.1
	3622	+ * max bandwidth (and much, much bigger bandwidths
	3623	+ * than that, actually).
	3624	+ *
	3625	+ * NOTE: Reducing link BW by 3% may not be precise
	3626	+ * because it may be a stream BT that increases by 3%, and so
	3627	+ * 1/1.03 = 0.970873 factor should have been used instead,
	3628	+ * but the difference is minimal and is in a safe direction,
	3629	+ * which all works well around potential ambiguity of DP 1.4a spec.
	3630	+ */
	3631	+ link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
	3632	+ link_bw_kbps, 32);
	3633	+ }
	3634	+
	3635	+ return link_bw_kbps;
	3636	+
	3637	+}
	3638	+
	3639	+const struct dc_link_settings *dc_link_get_link_cap(
	3640	+ const struct dc_link *link)
	3641	+{
	3642	+ if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
	3643	+ link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
	3644	+ return &link->preferred_link_setting;
	3645	+ return &link->verified_link_cap;
	3646	+}
	3647	+
	3648	+void dc_link_overwrite_extended_receiver_cap(
	3649	+ struct dc_link *link)
	3650	+{
	3651	+ dp_overwrite_extended_receiver_cap(link);
	3652	+}
	3653	+
	3654	+bool dc_link_is_fec_supported(const struct dc_link *link)
	3655	+{
	3656	+ return (dc_is_dp_signal(link->connector_signal) &&
	3657	+ link->link_enc->features.fec_supported &&
	3658	+ link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
	3659	+ !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
	3660	+}
	3661	+