~hc/RK356X_SDK_RELEASE.git

..	..	@@ -316,12 +316,12 @@
316	316	{
317	317	/*
318	318	* node id couldn't be 0 - the three MSB bits of
319		- * aperture shoudn't be 0
	319	+ * aperture shouldn't be 0
320	320	*/
321	321	pdd->lds_base = MAKE_LDS_APP_BASE_VI();
322	322	pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
323	323
324		- if (!pdd->dev->device_info->needs_iommu_device) {
	324	+ if (!pdd->dev->use_iommu_v2) {
325	325	/* dGPUs: SVM aperture starting at 0
326	326	* with small reserved space for kernel.
327	327	* Set them to CANONICAL addresses.
..	..	@@ -369,8 +369,13 @@
369	369
370	370	/Iterating over all devices/
371	371	while (kfd_topology_enum_kfd_devices(id, &dev) == 0) {
372		- if (!dev) {
373		- id++; /* Skip non GPU devices */
	372	+ if (!dev \|\| kfd_devcgroup_check_permission(dev)) {
	373	+ /* Skip non GPU devices and devices to which the
	374	+ * current process have no access to. Access can be
	375	+ * limited by placing the process in a specific
	376	+ * cgroup hierarchy
	377	+ */
	378	+ id++;
374	379	continue;
375	380	}
376	381
..	..	@@ -397,10 +402,21 @@
397	402	case CHIP_FIJI:
398	403	case CHIP_POLARIS10:
399	404	case CHIP_POLARIS11:
	405	+ case CHIP_POLARIS12:
	406	+ case CHIP_VEGAM:
400	407	kfd_init_apertures_vi(pdd, id);
401	408	break;
402	409	case CHIP_VEGA10:
	410	+ case CHIP_VEGA12:
	411	+ case CHIP_VEGA20:
403	412	case CHIP_RAVEN:
	413	+ case CHIP_RENOIR:
	414	+ case CHIP_ARCTURUS:
	415	+ case CHIP_NAVI10:
	416	+ case CHIP_NAVI12:
	417	+ case CHIP_NAVI14:
	418	+ case CHIP_SIENNA_CICHLID:
	419	+ case CHIP_NAVY_FLOUNDER:
404	420	kfd_init_apertures_v9(pdd, id);
405	421	break;
406	422	default:
..	..	@@ -409,7 +425,7 @@
409	425	return -EINVAL;
410	426	}
411	427
412		- if (!dev->device_info->needs_iommu_device) {
	428	+ if (!dev->use_iommu_v2) {
413	429	/* dGPUs: the reserved space for kernel
414	430	* before SVM
415	431	*/
..	..	@@ -432,5 +448,3 @@
432	448
433	449	return 0;
434	450	}
435		-
436		-