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| 67 | 67 | #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898) |
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| 68 | 68 | #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898) |
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| 69 | 69 | |
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| 70 | | -#define AMDGPU_NUM_OF_VMIDS 8 |
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| 71 | | - |
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| 72 | 70 | #define PIPEID(x) ((x) << 0) |
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| 73 | 71 | #define MEID(x) ((x) << 2) |
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| 74 | 72 | #define VMID(x) ((x) << 4) |
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| 332 | 330 | # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) |
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| 333 | 331 | # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) |
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| 334 | 332 | # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) |
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| 335 | | -#define PACKET3_AQUIRE_MEM 0x58 |
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| 333 | +#define PACKET3_ACQUIRE_MEM 0x58 |
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| 336 | 334 | #define PACKET3_REWIND 0x59 |
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| 337 | 335 | #define PACKET3_LOAD_UCONFIG_REG 0x5E |
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| 338 | 336 | #define PACKET3_LOAD_SH_REG 0x5F |
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