disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
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@@ -26,7 +26,7 @@
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  */
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 #include <linux/firmware.h>
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-#include <drm/drmP.h>
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+
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 #include "amdgpu.h"
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 #include "amdgpu_vce.h"
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 #include "vid.h"
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@@ -37,7 +37,6 @@
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 #include "gca/gfx_8_0_d.h"
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 #include "smu/smu_7_1_2_d.h"
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 #include "smu/smu_7_1_2_sh_mask.h"
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-#include "gca/gfx_8_0_d.h"
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 #include "gca/gfx_8_0_sh_mask.h"
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 #include "ivsrcid/ivsrcid_vislands30.h"
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@@ -423,7 +422,7 @@
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 	int r, i;
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 	/* VCE */
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-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
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+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
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 	if (r)
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 		return r;
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@@ -443,7 +442,8 @@
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 	for (i = 0; i < adev->vce.num_rings; i++) {
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 		ring = &adev->vce.ring[i];
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 		sprintf(ring->name, "vce%d", i);
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-		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
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+		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
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+				     AMDGPU_RING_PRIO_DEFAULT);
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 		if (r)
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 			return r;
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 	}
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@@ -474,15 +474,10 @@
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 	amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
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-	for (i = 0; i < adev->vce.num_rings; i++)
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-		adev->vce.ring[i].ready = false;
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-
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 	for (i = 0; i < adev->vce.num_rings; i++) {
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-		r = amdgpu_ring_test_ring(&adev->vce.ring[i]);
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+		r = amdgpu_ring_test_helper(&adev->vce.ring[i]);
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 		if (r)
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 			return r;
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-		else
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-			adev->vce.ring[i].ready = true;
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 	}
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 	DRM_INFO("VCE initialized successfully.\n");
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@@ -745,7 +740,7 @@
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 					  enum amd_clockgating_state state)
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 {
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
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+	bool enable = (state == AMD_CG_STATE_GATE);
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 	int i;
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 	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
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@@ -838,8 +833,12 @@
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 }
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 static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
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-		struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
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+				  struct amdgpu_job *job,
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+				  struct amdgpu_ib *ib,
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+				  uint32_t flags)
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 {
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+	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
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+
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 	amdgpu_ring_write(ring, VCE_CMD_IB_VM);
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 	amdgpu_ring_write(ring, vmid);
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 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
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@@ -896,6 +895,7 @@
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 	.align_mask = 0xf,
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 	.nop = VCE_CMD_NO_OP,
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 	.support_64bit_ptrs = false,
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+	.no_user_fence = true,
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 	.get_rptr = vce_v3_0_ring_get_rptr,
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 	.get_wptr = vce_v3_0_ring_get_wptr,
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 	.set_wptr = vce_v3_0_ring_set_wptr,
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@@ -919,6 +919,7 @@
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 	.align_mask = 0xf,
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 	.nop = VCE_CMD_NO_OP,
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 	.support_64bit_ptrs = false,
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+	.no_user_fence = true,
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 	.get_rptr = vce_v3_0_ring_get_rptr,
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 	.get_wptr = vce_v3_0_ring_get_wptr,
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 	.set_wptr = vce_v3_0_ring_set_wptr,