disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
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@@ -27,11 +27,8 @@
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 #include "nbio/nbio_6_1_default.h"
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 #include "nbio/nbio_6_1_offset.h"
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 #include "nbio/nbio_6_1_sh_mask.h"
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+#include "nbio/nbio_6_1_smn.h"
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 #include "vega10_enum.h"
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-
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-#define smnCPM_CONTROL                                                                                  0x11180460
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-#define smnPCIE_CNTL2                                                                                   0x11180070
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-#define smnPCIE_CONFIG_CNTL                                                                             0x11180044
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 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
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 {
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@@ -71,7 +68,7 @@
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 }
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 static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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-				  bool use_doorbell, int doorbell_index)
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+			bool use_doorbell, int doorbell_index, int doorbell_size)
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 {
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 	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
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 			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
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@@ -80,7 +77,7 @@
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 	if (use_doorbell) {
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 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
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-		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
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+		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
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 	} else
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 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
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@@ -121,7 +118,8 @@
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 	if (use_doorbell) {
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 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
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-		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
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+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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+						  BIF_IH_DOORBELL_RANGE, SIZE, 6);
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 	} else
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 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
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@@ -228,7 +226,7 @@
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 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
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 }
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-static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
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+const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
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 	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
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 	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
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 	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
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@@ -243,23 +241,6 @@
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 	.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
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 };
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-static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
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-{
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-	uint32_t reg;
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-
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-	reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER);
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-	if (reg & 1)
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-		adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
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-
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-	if (reg & 0x80000000)
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-		adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
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-
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-	if (!reg) {
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-		if (is_virtual_machine())	/* passthrough mode exclus sriov mod */
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-			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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-	}
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-}
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-
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 static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
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 {
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 	uint32_t def, data;
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@@ -270,10 +251,15 @@
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 	if (def != data)
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 		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
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+
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+	def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
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+	data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
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+
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+	if (def != data)
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+		WREG32_PCIE(smnPCIE_CI_CNTL, data);
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 }
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 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
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-	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
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 	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
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 	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
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 	.get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
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@@ -291,5 +277,4 @@
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 	.get_clockgating_state = nbio_v6_1_get_clockgating_state,
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 	.ih_control = nbio_v6_1_ih_control,
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 	.init_registers = nbio_v6_1_init_registers,
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-	.detect_hw_virt = nbio_v6_1_detect_hw_virt,
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 };