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hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
....@@ -20,12 +20,16 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  *
2222  */
23
+
2324 #include <linux/firmware.h>
24
-#include <drm/drmP.h>
25
+#include <linux/module.h>
26
+#include <linux/pci.h>
27
+
2528 #include <drm/drm_cache.h>
2629 #include "amdgpu.h"
2730 #include "gmc_v6_0.h"
2831 #include "amdgpu_ucode.h"
32
+#include "amdgpu_gem.h"
2933 
3034 #include "bif/bif_3_0_d.h"
3135 #include "bif/bif_3_0_sh_mask.h"
....@@ -56,17 +60,6 @@
5660 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
5761 #define MC_SEQ_MISC0__MT__HBM    0x60000000
5862 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
59
-
60
-
61
-static const u32 crtc_offsets[6] =
62
-{
63
-	SI_CRTC0_REGISTER_OFFSET,
64
-	SI_CRTC1_REGISTER_OFFSET,
65
-	SI_CRTC2_REGISTER_OFFSET,
66
-	SI_CRTC3_REGISTER_OFFSET,
67
-	SI_CRTC4_REGISTER_OFFSET,
68
-	SI_CRTC5_REGISTER_OFFSET
69
-};
7063 
7164 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
7265 {
....@@ -224,8 +217,8 @@
224217 	u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
225218 	base <<= 24;
226219 
227
-	amdgpu_device_vram_location(adev, &adev->gmc, base);
228
-	amdgpu_device_gart_location(adev, mc);
220
+	amdgpu_gmc_vram_location(adev, mc, base);
221
+	amdgpu_gmc_gart_location(adev, mc);
229222 }
230223 
231224 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
....@@ -358,7 +351,8 @@
358351 	return 0;
359352 }
360353 
361
-static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
354
+static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
355
+					uint32_t vmhub, uint32_t flush_type)
362356 {
363357 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
364358 }
....@@ -381,39 +375,18 @@
381375 	return pd_addr;
382376 }
383377 
384
-static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
385
-				uint32_t gpu_page_idx, uint64_t addr,
386
-				uint64_t flags)
387
-{
388
-	void __iomem *ptr = (void *)cpu_pt_addr;
389
-	uint64_t value;
390
-
391
-	value = addr & 0xFFFFFFFFFFFFF000ULL;
392
-	value |= flags;
393
-	writeq(value, ptr + (gpu_page_idx * 8));
394
-
395
-	return 0;
396
-}
397
-
398
-static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
399
-					  uint32_t flags)
400
-{
401
-	uint64_t pte_flag = 0;
402
-
403
-	if (flags & AMDGPU_VM_PAGE_READABLE)
404
-		pte_flag |= AMDGPU_PTE_READABLE;
405
-	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
406
-		pte_flag |= AMDGPU_PTE_WRITEABLE;
407
-	if (flags & AMDGPU_VM_PAGE_PRT)
408
-		pte_flag |= AMDGPU_PTE_PRT;
409
-
410
-	return pte_flag;
411
-}
412
-
413378 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
414379 				uint64_t *addr, uint64_t *flags)
415380 {
416381 	BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
382
+}
383
+
384
+static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev,
385
+				struct amdgpu_bo_va_mapping *mapping,
386
+				uint64_t *flags)
387
+{
388
+	*flags &= ~AMDGPU_PTE_EXECUTABLE;
389
+	*flags &= ~AMDGPU_PTE_PRT;
417390 }
418391 
419392 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
....@@ -494,16 +467,20 @@
494467 
495468 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
496469 {
470
+	uint64_t table_addr;
497471 	int r, i;
498472 	u32 field;
499473 
500
-	if (adev->gart.robj == NULL) {
474
+	if (adev->gart.bo == NULL) {
501475 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
502476 		return -EINVAL;
503477 	}
504478 	r = amdgpu_gart_table_vram_pin(adev);
505479 	if (r)
506480 		return r;
481
+
482
+	table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
483
+
507484 	/* Setup TLB control */
508485 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,
509486 	       (0xA << 7) |
....@@ -532,7 +509,7 @@
532509 	/* setup context0 */
533510 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
534511 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
535
-	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
512
+	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
536513 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
537514 			(u32)(adev->dummy_page_addr >> 12));
538515 	WREG32(mmVM_CONTEXT0_CNTL2, 0);
....@@ -556,10 +533,10 @@
556533 	for (i = 1; i < 16; i++) {
557534 		if (i < 8)
558535 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
559
-			       adev->gart.table_addr >> 12);
536
+			       table_addr >> 12);
560537 		else
561538 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
562
-			       adev->gart.table_addr >> 12);
539
+			       table_addr >> 12);
563540 	}
564541 
565542 	/* enable context1-15 */
....@@ -576,10 +553,10 @@
576553 	else
577554 		gmc_v6_0_set_fault_enable_default(adev, true);
578555 
579
-	gmc_v6_0_flush_gpu_tlb(adev, 0);
556
+	gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0);
580557 	dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
581558 		 (unsigned)(adev->gmc.gart_size >> 20),
582
-		 (unsigned long long)adev->gart.table_addr);
559
+		 (unsigned long long)table_addr);
583560 	adev->gart.ready = true;
584561 	return 0;
585562 }
....@@ -588,7 +565,7 @@
588565 {
589566 	int r;
590567 
591
-	if (adev->gart.robj) {
568
+	if (adev->gart.bo) {
592569 		dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
593570 		return 0;
594571 	}
....@@ -828,24 +805,22 @@
828805 	unsigned size;
829806 
830807 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
831
-		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
808
+		size = AMDGPU_VBIOS_VGA_ALLOCATION;
832809 	} else {
833810 		u32 viewport = RREG32(mmVIEWPORT_SIZE);
834811 		size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
835812 			REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
836813 			4);
837814 	}
838
-	/* return 0 if the pre-OS buffer uses up most of vram */
839
-	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
840
-		return 0;
841815 	return size;
842816 }
843817 
844818 static int gmc_v6_0_sw_init(void *handle)
845819 {
846820 	int r;
847
-	int dma_bits;
848821 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
822
+
823
+	adev->num_vmhubs = 1;
849824 
850825 	if (adev->flags & AMD_IS_APU) {
851826 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
....@@ -855,11 +830,11 @@
855830 		adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
856831 	}
857832 
858
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
833
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
859834 	if (r)
860835 		return r;
861836 
862
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
837
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
863838 	if (r)
864839 		return r;
865840 
....@@ -867,20 +842,12 @@
867842 
868843 	adev->gmc.mc_mask = 0xffffffffffULL;
869844 
870
-	adev->need_dma32 = false;
871
-	dma_bits = adev->need_dma32 ? 32 : 40;
872
-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
845
+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
873846 	if (r) {
874
-		adev->need_dma32 = true;
875
-		dma_bits = 32;
876
-		dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
847
+		dev_warn(adev->dev, "No suitable DMA available.\n");
848
+		return r;
877849 	}
878
-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
879
-	if (r) {
880
-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
881
-		dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
882
-	}
883
-	adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
850
+	adev->need_swiotlb = drm_need_swiotlb(40);
884851 
885852 	r = gmc_v6_0_init_microcode(adev);
886853 	if (r) {
....@@ -892,7 +859,7 @@
892859 	if (r)
893860 		return r;
894861 
895
-	adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
862
+	amdgpu_gmc_get_vbios_allocations(adev);
896863 
897864 	r = amdgpu_bo_init(adev);
898865 	if (r)
....@@ -908,7 +875,7 @@
908875 	 * amdgpu graphics/compute will use VMIDs 1-7
909876 	 * amdkfd will use VMIDs 8-15
910877 	 */
911
-	adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
878
+	adev->vm_manager.first_kfd_vmid = 8;
912879 	amdgpu_vm_manager_init(adev);
913880 
914881 	/* base offset of vram pages */
....@@ -1163,10 +1130,10 @@
11631130 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
11641131 	.flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
11651132 	.emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1166
-	.set_pte_pde = gmc_v6_0_set_pte_pde,
11671133 	.set_prt = gmc_v6_0_set_prt,
11681134 	.get_vm_pde = gmc_v6_0_get_vm_pde,
1169
-	.get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1135
+	.get_vm_pte = gmc_v6_0_get_vm_pte,
1136
+	.get_vbios_fb_size = gmc_v6_0_get_vbios_fb_size,
11701137 };
11711138 
11721139 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
....@@ -1176,8 +1143,7 @@
11761143 
11771144 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
11781145 {
1179
-	if (adev->gmc.gmc_funcs == NULL)
1180
-		adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1146
+	adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
11811147 }
11821148 
11831149 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)