| .. | .. |
|---|
| 3800 | 3800 | return r; |
|---|
| 3801 | 3801 | |
|---|
| 3802 | 3802 | r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); |
|---|
| 3803 | | - if (unlikely(r != 0)) |
|---|
| 3803 | + if (unlikely(r != 0)) { |
|---|
| 3804 | + amdgpu_bo_unreserve(ring->mqd_obj); |
|---|
| 3804 | 3805 | return r; |
|---|
| 3806 | + } |
|---|
| 3805 | 3807 | |
|---|
| 3806 | 3808 | gfx_v9_0_kiq_init_queue(ring); |
|---|
| 3807 | 3809 | amdgpu_bo_kunmap(ring->mqd_obj); |
|---|
| .. | .. |
|---|
| 3943 | 3945 | { |
|---|
| 3944 | 3946 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
|---|
| 3945 | 3947 | |
|---|
| 3946 | | - amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); |
|---|
| 3948 | + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
|---|
| 3949 | + amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); |
|---|
| 3947 | 3950 | amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); |
|---|
| 3948 | 3951 | amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); |
|---|
| 3949 | 3952 | |
|---|