disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
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@@ -24,63 +24,54 @@
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 #ifndef __AMDGPU_IH_H__
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 #define __AMDGPU_IH_H__
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-#include <linux/chash.h>
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-#include "soc15_ih_clientid.h"
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+/* Maximum number of IVs processed at once */
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+#define AMDGPU_IH_MAX_NUM_IVS	32
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 struct amdgpu_device;
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-
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-#define AMDGPU_IH_CLIENTID_LEGACY 0
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-#define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
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-
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-#define AMDGPU_PAGEFAULT_HASH_BITS 8
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-struct amdgpu_retryfault_hashtable {
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-	DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
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-	spinlock_t	lock;
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-	int		count;
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-};
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+struct amdgpu_iv_entry;
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 /*
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  * R6xx+ IH ring
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  */
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 struct amdgpu_ih_ring {
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-	struct amdgpu_bo	*ring_obj;
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-	volatile uint32_t	*ring;
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-	unsigned		rptr;
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 	unsigned		ring_size;
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-	uint64_t		gpu_addr;
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 	uint32_t		ptr_mask;
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-	atomic_t		lock;
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-	bool                    enabled;
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-	unsigned		wptr_offs;
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-	unsigned		rptr_offs;
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 	u32			doorbell_index;
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 	bool			use_doorbell;
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 	bool			use_bus_addr;
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-	dma_addr_t		rb_dma_addr; /* only used when use_bus_addr = true */
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-	struct amdgpu_retryfault_hashtable *faults;
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+
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+	struct amdgpu_bo	*ring_obj;
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+	volatile uint32_t	*ring;
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+	uint64_t		gpu_addr;
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+
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+	uint64_t		wptr_addr;
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+	volatile uint32_t	*wptr_cpu;
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+
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+	uint64_t		rptr_addr;
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+	volatile uint32_t	*rptr_cpu;
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+
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+	bool                    enabled;
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+	unsigned		rptr;
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+	atomic_t		lock;
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 };
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-#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
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-
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-struct amdgpu_iv_entry {
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-	unsigned client_id;
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-	unsigned src_id;
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-	unsigned ring_id;
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-	unsigned vmid;
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-	unsigned vmid_src;
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-	uint64_t timestamp;
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-	unsigned timestamp_src;
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-	unsigned pasid;
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-	unsigned pasid_src;
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-	unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
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-	const uint32_t *iv_entry;
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+/* provided by the ih block */
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+struct amdgpu_ih_funcs {
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+	/* ring read/write ptr handling, called from interrupt context */
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+	u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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+	void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
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+			  struct amdgpu_iv_entry *entry);
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+	void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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 };
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-int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
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-			bool use_bus_addr);
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-void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
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-int amdgpu_ih_process(struct amdgpu_device *adev);
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-int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key);
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-void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key);
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+#define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
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+#define amdgpu_ih_decode_iv(adev, iv) \
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+	(adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
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+#define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
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+
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+int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
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+			unsigned ring_size, bool use_bus_addr);
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+void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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+int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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 #endif