| .. | .. |
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| 27 | 27 | |
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| 28 | 28 | #include <linux/types.h> |
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| 29 | 29 | #include <linux/mm.h> |
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| 30 | | -#include <linux/mmu_context.h> |
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| 30 | +#include <linux/kthread.h> |
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| 31 | 31 | #include <linux/workqueue.h> |
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| 32 | 32 | #include <kgd_kfd_interface.h> |
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| 33 | 33 | #include <drm/ttm/ttm_execbuf_util.h> |
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| 34 | 34 | #include "amdgpu_sync.h" |
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| 35 | 35 | #include "amdgpu_vm.h" |
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| 36 | 36 | |
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| 37 | | -extern const struct kgd2kfd_calls *kgd2kfd; |
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| 37 | +extern uint64_t amdgpu_amdkfd_total_mem_size; |
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| 38 | 38 | |
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| 39 | 39 | struct amdgpu_device; |
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| 40 | 40 | |
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| .. | .. |
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| 58 | 58 | unsigned int mapped_to_gpu_memory; |
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| 59 | 59 | uint64_t va; |
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| 60 | 60 | |
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| 61 | | - uint32_t mapping_flags; |
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| 61 | + uint32_t alloc_flags; |
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| 62 | 62 | |
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| 63 | 63 | atomic_t invalid; |
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| 64 | 64 | struct amdkfd_process_info *process_info; |
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| 65 | | - struct page **user_pages; |
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| 66 | 65 | |
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| 67 | 66 | struct amdgpu_sync sync; |
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| 68 | 67 | |
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| 69 | 68 | bool aql_queue; |
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| 69 | + bool is_imported; |
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| 70 | 70 | }; |
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| 71 | 71 | |
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| 72 | 72 | /* KFD Memory Eviction */ |
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| .. | .. |
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| 77 | 77 | char timeline_name[TASK_COMM_LEN]; |
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| 78 | 78 | }; |
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| 79 | 79 | |
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| 80 | | -struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, |
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| 81 | | - struct mm_struct *mm); |
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| 82 | | -bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); |
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| 83 | | -struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); |
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| 80 | +struct amdgpu_kfd_dev { |
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| 81 | + struct kfd_dev *dev; |
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| 82 | + uint64_t vram_used; |
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| 83 | +}; |
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| 84 | + |
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| 85 | +enum kgd_engine_type { |
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| 86 | + KGD_ENGINE_PFP = 1, |
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| 87 | + KGD_ENGINE_ME, |
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| 88 | + KGD_ENGINE_CE, |
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| 89 | + KGD_ENGINE_MEC1, |
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| 90 | + KGD_ENGINE_MEC2, |
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| 91 | + KGD_ENGINE_RLC, |
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| 92 | + KGD_ENGINE_SDMA1, |
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| 93 | + KGD_ENGINE_SDMA2, |
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| 94 | + KGD_ENGINE_MAX |
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| 95 | +}; |
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| 96 | + |
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| 84 | 97 | |
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| 85 | 98 | struct amdkfd_process_info { |
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| 86 | 99 | /* List head of all VMs that belong to a KFD process */ |
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| .. | .. |
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| 107 | 120 | int amdgpu_amdkfd_init(void); |
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| 108 | 121 | void amdgpu_amdkfd_fini(void); |
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| 109 | 122 | |
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| 110 | | -void amdgpu_amdkfd_suspend(struct amdgpu_device *adev); |
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| 111 | | -int amdgpu_amdkfd_resume(struct amdgpu_device *adev); |
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| 123 | +void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); |
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| 124 | +int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev); |
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| 125 | +int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); |
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| 112 | 126 | void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, |
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| 113 | 127 | const void *ih_ring_entry); |
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| 114 | 128 | void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); |
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| 115 | 129 | void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); |
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| 116 | 130 | void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev); |
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| 117 | | - |
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| 118 | | -int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); |
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| 119 | 131 | int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, |
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| 120 | 132 | uint32_t vmid, uint64_t gpu_addr, |
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| 121 | 133 | uint32_t *ib_cmd, uint32_t ib_len); |
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| 122 | 134 | void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle); |
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| 123 | | - |
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| 124 | | -struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void); |
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| 125 | | -struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void); |
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| 126 | | -struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void); |
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| 135 | +bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd); |
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| 136 | +int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid); |
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| 137 | +int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid); |
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| 127 | 138 | |
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| 128 | 139 | bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); |
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| 129 | 140 | |
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| .. | .. |
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| 133 | 144 | |
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| 134 | 145 | void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd); |
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| 135 | 146 | |
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| 147 | +int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, |
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| 148 | + int queue_bit); |
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| 149 | + |
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| 150 | +struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, |
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| 151 | + struct mm_struct *mm); |
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| 152 | +#if IS_ENABLED(CONFIG_HSA_AMD) |
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| 153 | +bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); |
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| 154 | +struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); |
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| 155 | +int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); |
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| 156 | +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); |
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| 157 | +#else |
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| 158 | +static inline |
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| 159 | +bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) |
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| 160 | +{ |
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| 161 | + return false; |
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| 162 | +} |
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| 163 | + |
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| 164 | +static inline |
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| 165 | +struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) |
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| 166 | +{ |
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| 167 | + return NULL; |
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| 168 | +} |
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| 169 | + |
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| 170 | +static inline |
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| 171 | +int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) |
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| 172 | +{ |
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| 173 | + return 0; |
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| 174 | +} |
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| 175 | + |
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| 176 | +static inline |
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| 177 | +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) |
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| 178 | +{ |
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| 179 | + return 0; |
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| 180 | +} |
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| 181 | +#endif |
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| 136 | 182 | /* Shared API */ |
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| 137 | | -int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, |
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| 138 | | - void **mem_obj, uint64_t *gpu_addr, |
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| 139 | | - void **cpu_ptr, bool mqd_gfx9); |
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| 140 | | -void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj); |
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| 141 | | -void get_local_mem_info(struct kgd_dev *kgd, |
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| 142 | | - struct kfd_local_mem_info *mem_info); |
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| 143 | | -uint64_t get_gpu_clock_counter(struct kgd_dev *kgd); |
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| 183 | +int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, |
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| 184 | + void **mem_obj, uint64_t *gpu_addr, |
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| 185 | + void **cpu_ptr, bool mqd_gfx9); |
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| 186 | +void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj); |
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| 187 | +int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, void **mem_obj); |
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| 188 | +void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj); |
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| 189 | +int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); |
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| 190 | +int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); |
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| 191 | +uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, |
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| 192 | + enum kgd_engine_type type); |
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| 193 | +void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, |
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| 194 | + struct kfd_local_mem_info *mem_info); |
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| 195 | +uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd); |
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| 144 | 196 | |
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| 145 | | -uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd); |
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| 146 | | -void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info); |
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| 197 | +uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd); |
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| 198 | +void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info); |
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| 199 | +int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, |
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| 200 | + struct kgd_dev **dmabuf_kgd, |
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| 201 | + uint64_t *bo_size, void *metadata_buffer, |
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| 202 | + size_t buffer_size, uint32_t *metadata_size, |
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| 203 | + uint32_t *flags); |
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| 147 | 204 | uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd); |
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| 205 | +uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd); |
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| 206 | +uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd); |
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| 207 | +uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd); |
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| 208 | +uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd); |
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| 209 | +uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd); |
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| 210 | +int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd); |
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| 211 | +uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src); |
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| 148 | 212 | |
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| 213 | +/* Read user wptr from a specified user address space with page fault |
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| 214 | + * disabled. The memory must be pinned and mapped to the hardware when |
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| 215 | + * this is called in hqd_load functions, so it should never fault in |
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| 216 | + * the first place. This resolves a circular lock dependency involving |
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| 217 | + * four locks, including the DQM lock and mmap_lock. |
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| 218 | + */ |
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| 149 | 219 | #define read_user_wptr(mmptr, wptr, dst) \ |
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| 150 | 220 | ({ \ |
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| 151 | 221 | bool valid = false; \ |
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| 152 | 222 | if ((mmptr) && (wptr)) { \ |
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| 223 | + pagefault_disable(); \ |
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| 153 | 224 | if ((mmptr) == current->mm) { \ |
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| 154 | 225 | valid = !get_user((dst), (wptr)); \ |
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| 155 | | - } else if (current->mm == NULL) { \ |
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| 156 | | - use_mm(mmptr); \ |
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| 226 | + } else if (current->flags & PF_KTHREAD) { \ |
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| 227 | + kthread_use_mm(mmptr); \ |
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| 157 | 228 | valid = !get_user((dst), (wptr)); \ |
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| 158 | | - unuse_mm(mmptr); \ |
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| 229 | + kthread_unuse_mm(mmptr); \ |
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| 159 | 230 | } \ |
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| 231 | + pagefault_enable(); \ |
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| 160 | 232 | } \ |
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| 161 | 233 | valid; \ |
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| 162 | 234 | }) |
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| 163 | 235 | |
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| 164 | 236 | /* GPUVM API */ |
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| 165 | | -int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm, |
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| 166 | | - void **process_info, |
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| 167 | | - struct dma_fence **ef); |
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| 168 | | -int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd, |
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| 169 | | - struct file *filp, |
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| 237 | +int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, u32 pasid, |
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| 170 | 238 | void **vm, void **process_info, |
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| 171 | 239 | struct dma_fence **ef); |
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| 172 | | -void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, |
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| 173 | | - struct amdgpu_vm *vm); |
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| 240 | +int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd, |
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| 241 | + struct file *filp, u32 pasid, |
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| 242 | + void **vm, void **process_info, |
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| 243 | + struct dma_fence **ef); |
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| 174 | 244 | void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm); |
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| 175 | | -uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm); |
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| 245 | +void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm); |
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| 246 | +uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm); |
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| 176 | 247 | int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( |
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| 177 | 248 | struct kgd_dev *kgd, uint64_t va, uint64_t size, |
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| 178 | 249 | void *vm, struct kgd_mem **mem, |
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| 179 | 250 | uint64_t *offset, uint32_t flags); |
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| 180 | 251 | int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( |
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| 181 | | - struct kgd_dev *kgd, struct kgd_mem *mem); |
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| 252 | + struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size); |
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| 182 | 253 | int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( |
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| 183 | 254 | struct kgd_dev *kgd, struct kgd_mem *mem, void *vm); |
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| 184 | 255 | int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( |
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| .. | .. |
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| 189 | 260 | struct kgd_mem *mem, void **kptr, uint64_t *size); |
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| 190 | 261 | int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, |
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| 191 | 262 | struct dma_fence **ef); |
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| 192 | | - |
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| 193 | 263 | int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd, |
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| 194 | 264 | struct kfd_vm_fault_info *info); |
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| 195 | | - |
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| 265 | +int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, |
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| 266 | + struct dma_buf *dmabuf, |
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| 267 | + uint64_t va, void *vm, |
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| 268 | + struct kgd_mem **mem, uint64_t *size, |
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| 269 | + uint64_t *mmap_offset); |
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| 270 | +int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, |
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| 271 | + struct tile_config *config); |
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| 272 | +#if IS_ENABLED(CONFIG_HSA_AMD) |
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| 196 | 273 | void amdgpu_amdkfd_gpuvm_init_mem_limits(void); |
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| 197 | | -void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo); |
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| 274 | +void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, |
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| 275 | + struct amdgpu_vm *vm); |
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| 276 | +void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo); |
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| 277 | +#else |
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| 278 | +static inline |
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| 279 | +void amdgpu_amdkfd_gpuvm_init_mem_limits(void) |
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| 280 | +{ |
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| 281 | +} |
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| 198 | 282 | |
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| 283 | +static inline |
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| 284 | +void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, |
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| 285 | + struct amdgpu_vm *vm) |
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| 286 | +{ |
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| 287 | +} |
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| 288 | + |
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| 289 | +static inline |
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| 290 | +void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) |
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| 291 | +{ |
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| 292 | +} |
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| 293 | +#endif |
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| 294 | +/* KGD2KFD callbacks */ |
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| 295 | +int kgd2kfd_quiesce_mm(struct mm_struct *mm); |
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| 296 | +int kgd2kfd_resume_mm(struct mm_struct *mm); |
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| 297 | +int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, |
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| 298 | + struct dma_fence *fence); |
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| 299 | +#if IS_ENABLED(CONFIG_HSA_AMD) |
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| 300 | +int kgd2kfd_init(void); |
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| 301 | +void kgd2kfd_exit(void); |
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| 302 | +struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, |
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| 303 | + unsigned int asic_type, bool vf); |
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| 304 | +bool kgd2kfd_device_init(struct kfd_dev *kfd, |
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| 305 | + struct drm_device *ddev, |
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| 306 | + const struct kgd2kfd_shared_resources *gpu_resources); |
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| 307 | +void kgd2kfd_device_exit(struct kfd_dev *kfd); |
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| 308 | +void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); |
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| 309 | +int kgd2kfd_resume_iommu(struct kfd_dev *kfd); |
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| 310 | +int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); |
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| 311 | +int kgd2kfd_pre_reset(struct kfd_dev *kfd); |
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| 312 | +int kgd2kfd_post_reset(struct kfd_dev *kfd); |
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| 313 | +void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); |
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| 314 | +void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); |
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| 315 | +void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask); |
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| 316 | +#else |
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| 317 | +static inline int kgd2kfd_init(void) |
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| 318 | +{ |
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| 319 | + return -ENOENT; |
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| 320 | +} |
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| 321 | + |
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| 322 | +static inline void kgd2kfd_exit(void) |
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| 323 | +{ |
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| 324 | +} |
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| 325 | + |
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| 326 | +static inline |
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| 327 | +struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, |
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| 328 | + unsigned int asic_type, bool vf) |
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| 329 | +{ |
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| 330 | + return NULL; |
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| 331 | +} |
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| 332 | + |
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| 333 | +static inline |
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| 334 | +bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev, |
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| 335 | + const struct kgd2kfd_shared_resources *gpu_resources) |
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| 336 | +{ |
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| 337 | + return false; |
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| 338 | +} |
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| 339 | + |
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| 340 | +static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) |
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| 341 | +{ |
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| 342 | +} |
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| 343 | + |
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| 344 | +static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) |
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| 345 | +{ |
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| 346 | +} |
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| 347 | + |
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| 348 | +static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd) |
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| 349 | +{ |
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| 350 | + return 0; |
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| 351 | +} |
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| 352 | + |
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| 353 | +static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) |
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| 354 | +{ |
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| 355 | + return 0; |
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| 356 | +} |
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| 357 | + |
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| 358 | +static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd) |
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| 359 | +{ |
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| 360 | + return 0; |
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| 361 | +} |
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| 362 | + |
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| 363 | +static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) |
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| 364 | +{ |
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| 365 | + return 0; |
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| 366 | +} |
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| 367 | + |
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| 368 | +static inline |
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| 369 | +void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) |
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| 370 | +{ |
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| 371 | +} |
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| 372 | + |
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| 373 | +static inline |
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| 374 | +void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) |
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| 375 | +{ |
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| 376 | +} |
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| 377 | + |
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| 378 | +static inline |
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| 379 | +void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask) |
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| 380 | +{ |
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| 381 | +} |
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| 382 | +#endif |
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| 199 | 383 | #endif /* AMDGPU_AMDKFD_H_INCLUDED */ |
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