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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/gpu/arm/bifrost/mali_kbase_config_defaults.h
....@@ -1,7 +1,7 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
22 /*
33  *
4
- * (C) COPYRIGHT 2013-2021 ARM Limited. All rights reserved.
4
+ * (C) COPYRIGHT 2013-2023 ARM Limited. All rights reserved.
55  *
66  * This program is free software and is provided to you under the terms of the
77  * GNU General Public License version 2 as published by the Free Software
....@@ -31,33 +31,27 @@
3131 #include <mali_kbase_config_platform.h>
3232 
3333 enum {
34
-	/**
35
-	 * Use unrestricted Address ID width on the AXI bus.
36
-	 */
34
+	/* Use unrestricted Address ID width on the AXI bus. */
3735 	KBASE_AID_32 = 0x0,
3836 
39
-	/**
40
-	 * Restrict GPU to a half of maximum Address ID count.
37
+	/* Restrict GPU to a half of maximum Address ID count.
4138 	 * This will reduce performance, but reduce bus load due to GPU.
4239 	 */
4340 	KBASE_AID_16 = 0x3,
4441 
45
-	/**
46
-	 * Restrict GPU to a quarter of maximum Address ID count.
42
+	/* Restrict GPU to a quarter of maximum Address ID count.
4743 	 * This will reduce performance, but reduce bus load due to GPU.
4844 	 */
49
-	KBASE_AID_8  = 0x2,
45
+	KBASE_AID_8 = 0x2,
5046 
51
-	/**
52
-	 * Restrict GPU to an eighth of maximum Address ID count.
47
+	/* Restrict GPU to an eighth of maximum Address ID count.
5348 	 * This will reduce performance, but reduce bus load due to GPU.
5449 	 */
55
-	KBASE_AID_4  = 0x1
50
+	KBASE_AID_4 = 0x1
5651 };
5752 
5853 enum {
59
-	/**
60
-	 * Use unrestricted Address ID width on the AXI bus.
54
+	/* Use unrestricted Address ID width on the AXI bus.
6155 	 * Restricting ID width will reduce performance & bus load due to GPU.
6256 	 */
6357 	KBASE_3BIT_AID_32 = 0x0,
....@@ -78,21 +72,30 @@
7872 	KBASE_3BIT_AID_12 = 0x5,
7973 
8074 	/* Restrict GPU to 1/4 of maximum Address ID count. */
81
-	KBASE_3BIT_AID_8  = 0x6,
75
+	KBASE_3BIT_AID_8 = 0x6,
8276 
8377 	/* Restrict GPU to 1/8 of maximum Address ID count. */
84
-	KBASE_3BIT_AID_4  = 0x7
78
+	KBASE_3BIT_AID_4 = 0x7
8579 };
8680 
87
-/**
88
- * Default period for DVFS sampling (can be overridden by platform header)
81
+#if MALI_USE_CSF
82
+/*
83
+ * Default value for the TIMER register of the IPA Control interface,
84
+ * expressed in milliseconds.
85
+ *
86
+ * The chosen value is a trade off between two requirements: the IPA Control
87
+ * interface should sample counters with a resolution in the order of
88
+ * milliseconds, while keeping GPU overhead as limited as possible.
8989  */
90
+#define IPA_CONTROL_TIMER_DEFAULT_VALUE_MS ((u32)10) /* 10 milliseconds */
91
+#endif /* MALI_USE_CSF */
92
+
93
+/* Default period for DVFS sampling (can be overridden by platform header) */
9094 #ifndef DEFAULT_PM_DVFS_PERIOD
9195 #define DEFAULT_PM_DVFS_PERIOD 100 /* 100ms */
9296 #endif
9397 
94
-/**
95
- * Power Management poweroff tick granuality. This is in nanoseconds to
98
+/* Power Management poweroff tick granuality. This is in nanoseconds to
9699  * allow HR timer support (can be overridden by platform header).
97100  *
98101  * On each scheduling tick, the power manager core may decide to:
....@@ -103,82 +106,134 @@
103106 #define DEFAULT_PM_GPU_POWEROFF_TICK_NS (400000) /* 400us */
104107 #endif
105108 
106
-/**
107
- * Power Manager number of ticks before shader cores are powered off
109
+/* Power Manager number of ticks before shader cores are powered off
108110  * (can be overridden by platform header).
109111  */
110112 #ifndef DEFAULT_PM_POWEROFF_TICK_SHADER
111113 #define DEFAULT_PM_POWEROFF_TICK_SHADER (2) /* 400-800us */
112114 #endif
113115 
114
-/**
115
- * Default scheduling tick granuality (can be overridden by platform header)
116
- */
116
+/* Default scheduling tick granuality (can be overridden by platform header) */
117117 #ifndef DEFAULT_JS_SCHEDULING_PERIOD_NS
118118 #define DEFAULT_JS_SCHEDULING_PERIOD_NS    (100000000u) /* 100ms */
119119 #endif
120120 
121
-/**
122
- * Default minimum number of scheduling ticks before jobs are soft-stopped.
121
+/* Default minimum number of scheduling ticks before jobs are soft-stopped.
123122  *
124123  * This defines the time-slice for a job (which may be different from that of a
125124  * context)
126125  */
127126 #define DEFAULT_JS_SOFT_STOP_TICKS       (1) /* 100ms-200ms */
128127 
129
-/**
130
- * Default minimum number of scheduling ticks before CL jobs are soft-stopped.
131
- */
128
+/* Default minimum number of scheduling ticks before CL jobs are soft-stopped. */
132129 #define DEFAULT_JS_SOFT_STOP_TICKS_CL    (1) /* 100ms-200ms */
133130 
134
-/**
135
- * Default minimum number of scheduling ticks before jobs are hard-stopped
136
- */
131
+/* Default minimum number of scheduling ticks before jobs are hard-stopped */
137132 #define DEFAULT_JS_HARD_STOP_TICKS_SS    (50) /* 5s */
138133 
139
-/**
140
- * Default minimum number of scheduling ticks before CL jobs are hard-stopped.
141
- */
134
+/* Default minimum number of scheduling ticks before CL jobs are hard-stopped. */
142135 #define DEFAULT_JS_HARD_STOP_TICKS_CL    (50) /* 5s */
143136 
144
-/**
145
- * Default minimum number of scheduling ticks before jobs are hard-stopped
137
+/* Default minimum number of scheduling ticks before jobs are hard-stopped
146138  * during dumping
147139  */
148140 #define DEFAULT_JS_HARD_STOP_TICKS_DUMPING   (15000) /* 1500s */
149141 
150
-/**
151
- * Default timeout for some software jobs, after which the software event wait
142
+/* Default timeout for some software jobs, after which the software event wait
152143  * jobs will be cancelled.
153144  */
154145 #define DEFAULT_JS_SOFT_JOB_TIMEOUT (3000) /* 3s */
155146 
156
-/**
157
- * Default minimum number of scheduling ticks before the GPU is reset to clear a
147
+/* Default minimum number of scheduling ticks before the GPU is reset to clear a
158148  * "stuck" job
159149  */
160150 #define DEFAULT_JS_RESET_TICKS_SS           (55) /* 5.5s */
161151 
162
-/**
163
- * Default minimum number of scheduling ticks before the GPU is reset to clear a
152
+/* Default minimum number of scheduling ticks before the GPU is reset to clear a
164153  * "stuck" CL job.
165154  */
166155 #define DEFAULT_JS_RESET_TICKS_CL        (55) /* 5.5s */
167156 
168
-/**
169
- * Default minimum number of scheduling ticks before the GPU is reset to clear a
157
+/* Default minimum number of scheduling ticks before the GPU is reset to clear a
170158  * "stuck" job during dumping.
171159  */
172160 #define DEFAULT_JS_RESET_TICKS_DUMPING   (15020) /* 1502s */
173161 
174
-/**
175
- * Default number of milliseconds given for other jobs on the GPU to be
162
+/* Nominal reference frequency that was used to obtain all following
163
+ * <...>_TIMEOUT_CYCLES macros, in kHz.
164
+ *
165
+ * Timeouts are scaled based on the relation between this value and the lowest
166
+ * GPU clock frequency.
167
+ */
168
+#define DEFAULT_REF_TIMEOUT_FREQ_KHZ (100000)
169
+
170
+#if MALI_USE_CSF
171
+/* Waiting timeout for status change acknowledgment, in clock cycles.
172
+ *
173
+ * This is also the default timeout to be used when an invalid timeout
174
+ * selector is used to retrieve the timeout on CSF GPUs.
175
+ *
176
+ * Based on 75000ms timeout at nominal 100MHz, as is required for Android - based
177
+ * on scaling from a 50MHz GPU system.
178
+ */
179
+#define CSF_FIRMWARE_TIMEOUT_CYCLES (7500000000ull)
180
+
181
+/* Timeout in clock cycles for GPU Power Management to reach the desired
182
+ * Shader, L2 and MCU state.
183
+ *
184
+ * Based on 2500ms timeout at nominal 100MHz, scaled from a 50MHz GPU system.
185
+ */
186
+#define CSF_PM_TIMEOUT_CYCLES (250000000)
187
+
188
+/* Waiting timeout in clock cycles for GPU reset to complete.
189
+ *
190
+ * Based on 2500ms timeout at 100MHz, scaled from a 50MHz GPU system
191
+ */
192
+#define CSF_GPU_RESET_TIMEOUT_CYCLES (250000000)
193
+
194
+/* Waiting timeout in clock cycles for all active CSGs to be suspended.
195
+ *
196
+ * Based on 1500ms timeout at 100MHz, scaled from a 50MHz GPU system.
197
+ */
198
+#define CSF_CSG_SUSPEND_TIMEOUT_CYCLES (150000000)
199
+
200
+/* Waiting timeout in clock cycles for GPU firmware to boot.
201
+ *
202
+ * Based on 250ms timeout at 100MHz, scaled from a 50MHz GPU system.
203
+ */
204
+#define CSF_FIRMWARE_BOOT_TIMEOUT_CYCLES (25000000)
205
+
206
+/* Waiting timeout for a ping request to be acknowledged, in clock cycles.
207
+ *
208
+ * Based on 6000ms timeout at 100MHz, scaled from a 50MHz GPU system.
209
+ */
210
+#define CSF_FIRMWARE_PING_TIMEOUT_CYCLES (600000000ull)
211
+
212
+#else /* MALI_USE_CSF */
213
+
214
+/* A default timeout in clock cycles to be used when an invalid timeout
215
+ * selector is used to retrieve the timeout, on JM GPUs.
216
+ */
217
+#define JM_DEFAULT_TIMEOUT_CYCLES (150000000)
218
+
219
+/* Default number of milliseconds given for other jobs on the GPU to be
176220  * soft-stopped when the GPU needs to be reset.
177221  */
178
-#define DEFAULT_RESET_TIMEOUT_MS (3000) /* 3s */
222
+#define JM_DEFAULT_RESET_TIMEOUT_MS (1) /* 1 ms */
179223 
180
-/**
181
- * Default timeslice that a context is scheduled in for, in nanoseconds.
224
+/* Default timeout in clock cycles to be used when checking if JS_COMMAND_NEXT
225
+ * is updated on HW side so a Job Slot is considered free.
226
+ * This timeout will only take effect on GPUs with low value for the minimum
227
+ * GPU clock frequency (<= 100MHz).
228
+ *
229
+ * Based on 1ms timeout at 100MHz. Will default to 0ms on GPUs with higher
230
+ * value for minimum GPU clock frequency.
231
+ */
232
+#define JM_DEFAULT_JS_FREE_TIMEOUT_CYCLES (100000)
233
+
234
+#endif /* MALI_USE_CSF */
235
+
236
+/* Default timeslice that a context is scheduled in for, in nanoseconds.
182237  *
183238  * When a context has used up this amount of time across its jobs, it is
184239  * scheduled out to let another run.
....@@ -188,16 +243,14 @@
188243  */
189244 #define DEFAULT_JS_CTX_TIMESLICE_NS (50000000) /* 50ms */
190245 
191
-/**
192
- * Maximum frequency (in kHz) that the GPU can be clocked. For some platforms
246
+/* Maximum frequency (in kHz) that the GPU can be clocked. For some platforms
193247  * this isn't available, so we simply define a dummy value here. If devfreq
194248  * is enabled the value will be read from there, otherwise this should be
195249  * overridden by defining GPU_FREQ_KHZ_MAX in the platform file.
196250  */
197251 #define DEFAULT_GPU_FREQ_KHZ_MAX (5000)
198252 
199
-/**
200
- * Default timeout for task execution on an endpoint
253
+/* Default timeout for task execution on an endpoint
201254  *
202255  * Number of GPU clock cycles before the driver terminates a task that is
203256  * making no forward progress on an endpoint (e.g. shader core).
....@@ -206,8 +259,7 @@
206259  */
207260 #define DEFAULT_PROGRESS_TIMEOUT ((u64)5 * 500 * 1024 * 1024)
208261 
209
-/**
210
- * Default threshold at which to switch to incremental rendering
262
+/* Default threshold at which to switch to incremental rendering
211263  *
212264  * Fraction of the maximum size of an allocation that grows on GPU page fault
213265  * that can be used up before the driver switches to incremental rendering,
....@@ -215,5 +267,12 @@
215267  */
216268 #define DEFAULT_IR_THRESHOLD (192)
217269 
270
+/* Waiting time in clock cycles for the completion of a MMU operation.
271
+ *
272
+ * Ideally 1.6M GPU cycles required for the L2 cache (512KiB slice) flush.
273
+ *
274
+ * As a pessimistic value, 50M GPU cycles ( > 30 times bigger ) is chosen.
275
+ * It corresponds to 0.5s in GPU @ 100Mhz.
276
+ */
277
+#define MMU_AS_INACTIVE_WAIT_TIMEOUT_CYCLES ((u64)50 * 1024 * 1024)
218278 #endif /* _KBASE_CONFIG_DEFAULTS_H_ */
219
-