~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,7 +1,7 @@
1	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	2	/*
3	3	*
4		- * (C) COPYRIGHT 2014-2021 ARM Limited. All rights reserved.
	4	+ * (C) COPYRIGHT 2014-2023 ARM Limited. All rights reserved.
5	5	*
6	6	* This program is free software and is provided to you under the terms of the
7	7	* GNU General Public License version 2 as published by the Free Software
..	..	@@ -59,14 +59,22 @@
59	59	BASE_HW_ISSUE_TTRX_3464,
60	60	BASE_HW_ISSUE_TTRX_3485,
61	61	BASE_HW_ISSUE_GPU2019_3212,
	62	+ BASE_HW_ISSUE_TURSEHW_1997,
	63	+ BASE_HW_ISSUE_GPU2019_3878,
	64	+ BASE_HW_ISSUE_TURSEHW_2716,
	65	+ BASE_HW_ISSUE_GPU2019_3901,
	66	+ BASE_HW_ISSUE_GPU2021PRO_290,
	67	+ BASE_HW_ISSUE_TITANHW_2710,
	68	+ BASE_HW_ISSUE_TITANHW_2679,
	69	+ BASE_HW_ISSUE_GPU2022PRO_148,
62	70	BASE_HW_ISSUE_END
63	71	};
64	72
65		-static const enum base_hw_issue base_hw_issues_generic[] = {
	73	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_generic[] = {
66	74	BASE_HW_ISSUE_END
67	75	};
68	76
69		-static const enum base_hw_issue base_hw_issues_tMIx_r0p0_05dev0[] = {
	77	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p0_05dev0[] = {
70	78	BASE_HW_ISSUE_9435,
71	79	BASE_HW_ISSUE_10682,
72	80	BASE_HW_ISSUE_11054,
..	..	@@ -83,10 +91,12 @@
83	91	BASE_HW_ISSUE_TSIX_2033,
84	92	BASE_HW_ISSUE_TTRX_921,
85	93	BASE_HW_ISSUE_GPU2017_1336,
	94	+ BASE_HW_ISSUE_TITANHW_2710,
	95	+ BASE_HW_ISSUE_GPU2022PRO_148,
86	96	BASE_HW_ISSUE_END
87	97	};
88	98
89		-static const enum base_hw_issue base_hw_issues_tMIx_r0p0[] = {
	99	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p0[] = {
90	100	BASE_HW_ISSUE_9435,
91	101	BASE_HW_ISSUE_10682,
92	102	BASE_HW_ISSUE_11054,
..	..	@@ -103,10 +113,12 @@
103	113	BASE_HW_ISSUE_TSIX_2033,
104	114	BASE_HW_ISSUE_TTRX_921,
105	115	BASE_HW_ISSUE_GPU2017_1336,
	116	+ BASE_HW_ISSUE_TITANHW_2710,
	117	+ BASE_HW_ISSUE_GPU2022PRO_148,
106	118	BASE_HW_ISSUE_END
107	119	};
108	120
109		-static const enum base_hw_issue base_hw_issues_tMIx_r0p1[] = {
	121	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p1[] = {
110	122	BASE_HW_ISSUE_9435,
111	123	BASE_HW_ISSUE_10682,
112	124	BASE_HW_ISSUE_11054,
..	..	@@ -123,10 +135,12 @@
123	135	BASE_HW_ISSUE_TSIX_2033,
124	136	BASE_HW_ISSUE_TTRX_921,
125	137	BASE_HW_ISSUE_GPU2017_1336,
	138	+ BASE_HW_ISSUE_TITANHW_2710,
	139	+ BASE_HW_ISSUE_GPU2022PRO_148,
126	140	BASE_HW_ISSUE_END
127	141	};
128	142
129		-static const enum base_hw_issue base_hw_issues_model_tMIx[] = {
	143	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tMIx[] = {
130	144	BASE_HW_ISSUE_5736,
131	145	BASE_HW_ISSUE_9435,
132	146	BASE_HW_ISSUE_TMIX_7891,
..	..	@@ -138,10 +152,12 @@
138	152	BASE_HW_ISSUE_TMIX_8343,
139	153	BASE_HW_ISSUE_TMIX_8456,
140	154	BASE_HW_ISSUE_TSIX_2033,
	155	+ BASE_HW_ISSUE_TITANHW_2710,
	156	+ BASE_HW_ISSUE_GPU2022PRO_148,
141	157	BASE_HW_ISSUE_END
142	158	};
143	159
144		-static const enum base_hw_issue base_hw_issues_tHEx_r0p0[] = {
	160	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p0[] = {
145	161	BASE_HW_ISSUE_9435,
146	162	BASE_HW_ISSUE_10682,
147	163	BASE_HW_ISSUE_11054,
..	..	@@ -151,10 +167,12 @@
151	167	BASE_HW_ISSUE_TSIX_2033,
152	168	BASE_HW_ISSUE_TTRX_921,
153	169	BASE_HW_ISSUE_GPU2017_1336,
	170	+ BASE_HW_ISSUE_TITANHW_2710,
	171	+ BASE_HW_ISSUE_GPU2022PRO_148,
154	172	BASE_HW_ISSUE_END
155	173	};
156	174
157		-static const enum base_hw_issue base_hw_issues_tHEx_r0p1[] = {
	175	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p1[] = {
158	176	BASE_HW_ISSUE_9435,
159	177	BASE_HW_ISSUE_10682,
160	178	BASE_HW_ISSUE_11054,
..	..	@@ -164,10 +182,12 @@
164	182	BASE_HW_ISSUE_TSIX_2033,
165	183	BASE_HW_ISSUE_TTRX_921,
166	184	BASE_HW_ISSUE_GPU2017_1336,
	185	+ BASE_HW_ISSUE_TITANHW_2710,
	186	+ BASE_HW_ISSUE_GPU2022PRO_148,
167	187	BASE_HW_ISSUE_END
168	188	};
169	189
170		-static const enum base_hw_issue base_hw_issues_tHEx_r0p2[] = {
	190	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p2[] = {
171	191	BASE_HW_ISSUE_9435,
172	192	BASE_HW_ISSUE_10682,
173	193	BASE_HW_ISSUE_11054,
..	..	@@ -177,10 +197,12 @@
177	197	BASE_HW_ISSUE_TSIX_2033,
178	198	BASE_HW_ISSUE_TTRX_921,
179	199	BASE_HW_ISSUE_GPU2017_1336,
	200	+ BASE_HW_ISSUE_TITANHW_2710,
	201	+ BASE_HW_ISSUE_GPU2022PRO_148,
180	202	BASE_HW_ISSUE_END
181	203	};
182	204
183		-static const enum base_hw_issue base_hw_issues_tHEx_r0p3[] = {
	205	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p3[] = {
184	206	BASE_HW_ISSUE_9435,
185	207	BASE_HW_ISSUE_10682,
186	208	BASE_HW_ISSUE_TMIX_7891,
..	..	@@ -189,20 +211,24 @@
189	211	BASE_HW_ISSUE_TSIX_2033,
190	212	BASE_HW_ISSUE_TTRX_921,
191	213	BASE_HW_ISSUE_GPU2017_1336,
	214	+ BASE_HW_ISSUE_TITANHW_2710,
	215	+ BASE_HW_ISSUE_GPU2022PRO_148,
192	216	BASE_HW_ISSUE_END
193	217	};
194	218
195		-static const enum base_hw_issue base_hw_issues_model_tHEx[] = {
	219	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tHEx[] = {
196	220	BASE_HW_ISSUE_5736,
197	221	BASE_HW_ISSUE_9435,
198	222	BASE_HW_ISSUE_TMIX_7891,
199	223	BASE_HW_ISSUE_TMIX_8042,
200	224	BASE_HW_ISSUE_TMIX_8133,
201	225	BASE_HW_ISSUE_TSIX_2033,
	226	+ BASE_HW_ISSUE_TITANHW_2710,
	227	+ BASE_HW_ISSUE_GPU2022PRO_148,
202	228	BASE_HW_ISSUE_END
203	229	};
204	230
205		-static const enum base_hw_issue base_hw_issues_tSIx_r0p0[] = {
	231	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r0p0[] = {
206	232	BASE_HW_ISSUE_9435,
207	233	BASE_HW_ISSUE_11054,
208	234	BASE_HW_ISSUE_TMIX_8133,
..	..	@@ -212,10 +238,12 @@
212	238	BASE_HW_ISSUE_TTRX_921,
213	239	BASE_HW_ISSUE_GPU2017_1336,
214	240	BASE_HW_ISSUE_TTRX_3464,
	241	+ BASE_HW_ISSUE_TITANHW_2710,
	242	+ BASE_HW_ISSUE_GPU2022PRO_148,
215	243	BASE_HW_ISSUE_END
216	244	};
217	245
218		-static const enum base_hw_issue base_hw_issues_tSIx_r0p1[] = {
	246	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r0p1[] = {
219	247	BASE_HW_ISSUE_9435,
220	248	BASE_HW_ISSUE_11054,
221	249	BASE_HW_ISSUE_TMIX_8133,
..	..	@@ -225,10 +253,12 @@
225	253	BASE_HW_ISSUE_TTRX_921,
226	254	BASE_HW_ISSUE_GPU2017_1336,
227	255	BASE_HW_ISSUE_TTRX_3464,
	256	+ BASE_HW_ISSUE_TITANHW_2710,
	257	+ BASE_HW_ISSUE_GPU2022PRO_148,
228	258	BASE_HW_ISSUE_END
229	259	};
230	260
231		-static const enum base_hw_issue base_hw_issues_tSIx_r1p0[] = {
	261	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r1p0[] = {
232	262	BASE_HW_ISSUE_9435,
233	263	BASE_HW_ISSUE_11054,
234	264	BASE_HW_ISSUE_TMIX_8133,
..	..	@@ -237,10 +267,12 @@
237	267	BASE_HW_ISSUE_TTRX_921,
238	268	BASE_HW_ISSUE_GPU2017_1336,
239	269	BASE_HW_ISSUE_TTRX_3464,
	270	+ BASE_HW_ISSUE_TITANHW_2710,
	271	+ BASE_HW_ISSUE_GPU2022PRO_148,
240	272	BASE_HW_ISSUE_END
241	273	};
242	274
243		-static const enum base_hw_issue base_hw_issues_tSIx_r1p1[] = {
	275	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r1p1[] = {
244	276	BASE_HW_ISSUE_9435,
245	277	BASE_HW_ISSUE_TMIX_8133,
246	278	BASE_HW_ISSUE_TSIX_1116,
..	..	@@ -248,20 +280,24 @@
248	280	BASE_HW_ISSUE_TTRX_921,
249	281	BASE_HW_ISSUE_GPU2017_1336,
250	282	BASE_HW_ISSUE_TTRX_3464,
	283	+ BASE_HW_ISSUE_TITANHW_2710,
	284	+ BASE_HW_ISSUE_GPU2022PRO_148,
251	285	BASE_HW_ISSUE_END
252	286	};
253	287
254		-static const enum base_hw_issue base_hw_issues_model_tSIx[] = {
	288	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tSIx[] = {
255	289	BASE_HW_ISSUE_5736,
256	290	BASE_HW_ISSUE_9435,
257	291	BASE_HW_ISSUE_TMIX_8133,
258	292	BASE_HW_ISSUE_TSIX_1116,
259	293	BASE_HW_ISSUE_TSIX_2033,
260	294	BASE_HW_ISSUE_TTRX_3464,
	295	+ BASE_HW_ISSUE_TITANHW_2710,
	296	+ BASE_HW_ISSUE_GPU2022PRO_148,
261	297	BASE_HW_ISSUE_END
262	298	};
263	299
264		-static const enum base_hw_issue base_hw_issues_tDVx_r0p0[] = {
	300	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tDVx_r0p0[] = {
265	301	BASE_HW_ISSUE_9435,
266	302	BASE_HW_ISSUE_TMIX_8133,
267	303	BASE_HW_ISSUE_TSIX_1116,
..	..	@@ -269,20 +305,24 @@
269	305	BASE_HW_ISSUE_TTRX_921,
270	306	BASE_HW_ISSUE_GPU2017_1336,
271	307	BASE_HW_ISSUE_TTRX_3464,
	308	+ BASE_HW_ISSUE_TITANHW_2710,
	309	+ BASE_HW_ISSUE_GPU2022PRO_148,
272	310	BASE_HW_ISSUE_END
273	311	};
274	312
275		-static const enum base_hw_issue base_hw_issues_model_tDVx[] = {
	313	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tDVx[] = {
276	314	BASE_HW_ISSUE_5736,
277	315	BASE_HW_ISSUE_9435,
278	316	BASE_HW_ISSUE_TMIX_8133,
279	317	BASE_HW_ISSUE_TSIX_1116,
280	318	BASE_HW_ISSUE_TSIX_2033,
281	319	BASE_HW_ISSUE_TTRX_3464,
	320	+ BASE_HW_ISSUE_TITANHW_2710,
	321	+ BASE_HW_ISSUE_GPU2022PRO_148,
282	322	BASE_HW_ISSUE_END
283	323	};
284	324
285		-static const enum base_hw_issue base_hw_issues_tNOx_r0p0[] = {
	325	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNOx_r0p0[] = {
286	326	BASE_HW_ISSUE_9435,
287	327	BASE_HW_ISSUE_TMIX_8133,
288	328	BASE_HW_ISSUE_TSIX_1116,
..	..	@@ -291,20 +331,24 @@
291	331	BASE_HW_ISSUE_TTRX_921,
292	332	BASE_HW_ISSUE_GPU2017_1336,
293	333	BASE_HW_ISSUE_TTRX_3464,
	334	+ BASE_HW_ISSUE_TITANHW_2710,
	335	+ BASE_HW_ISSUE_GPU2022PRO_148,
294	336	BASE_HW_ISSUE_END
295	337	};
296	338
297		-static const enum base_hw_issue base_hw_issues_model_tNOx[] = {
	339	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tNOx[] = {
298	340	BASE_HW_ISSUE_5736,
299	341	BASE_HW_ISSUE_9435,
300	342	BASE_HW_ISSUE_TMIX_8133,
301	343	BASE_HW_ISSUE_TSIX_1116,
302	344	BASE_HW_ISSUE_TSIX_2033,
303	345	BASE_HW_ISSUE_TTRX_3464,
	346	+ BASE_HW_ISSUE_TITANHW_2710,
	347	+ BASE_HW_ISSUE_GPU2022PRO_148,
304	348	BASE_HW_ISSUE_END
305	349	};
306	350
307		-static const enum base_hw_issue base_hw_issues_tGOx_r0p0[] = {
	351	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGOx_r0p0[] = {
308	352	BASE_HW_ISSUE_9435,
309	353	BASE_HW_ISSUE_TMIX_8133,
310	354	BASE_HW_ISSUE_TSIX_1116,
..	..	@@ -313,10 +357,12 @@
313	357	BASE_HW_ISSUE_TTRX_921,
314	358	BASE_HW_ISSUE_GPU2017_1336,
315	359	BASE_HW_ISSUE_TTRX_3464,
	360	+ BASE_HW_ISSUE_TITANHW_2710,
	361	+ BASE_HW_ISSUE_GPU2022PRO_148,
316	362	BASE_HW_ISSUE_END
317	363	};
318	364
319		-static const enum base_hw_issue base_hw_issues_tGOx_r1p0[] = {
	365	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGOx_r1p0[] = {
320	366	BASE_HW_ISSUE_9435,
321	367	BASE_HW_ISSUE_TMIX_8133,
322	368	BASE_HW_ISSUE_TSIX_1116,
..	..	@@ -325,20 +371,24 @@
325	371	BASE_HW_ISSUE_TTRX_921,
326	372	BASE_HW_ISSUE_GPU2017_1336,
327	373	BASE_HW_ISSUE_TTRX_3464,
	374	+ BASE_HW_ISSUE_TITANHW_2710,
	375	+ BASE_HW_ISSUE_GPU2022PRO_148,
328	376	BASE_HW_ISSUE_END
329	377	};
330	378
331		-static const enum base_hw_issue base_hw_issues_model_tGOx[] = {
	379	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tGOx[] = {
332	380	BASE_HW_ISSUE_5736,
333	381	BASE_HW_ISSUE_9435,
334	382	BASE_HW_ISSUE_TMIX_8133,
335	383	BASE_HW_ISSUE_TSIX_1116,
336	384	BASE_HW_ISSUE_TSIX_2033,
337	385	BASE_HW_ISSUE_TTRX_3464,
	386	+ BASE_HW_ISSUE_TITANHW_2710,
	387	+ BASE_HW_ISSUE_GPU2022PRO_148,
338	388	BASE_HW_ISSUE_END
339	389	};
340	390
341		-static const enum base_hw_issue base_hw_issues_tTRx_r0p0[] = {
	391	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p0[] = {
342	392	BASE_HW_ISSUE_9435,
343	393	BASE_HW_ISSUE_TSIX_2033,
344	394	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -351,10 +401,12 @@
351	401	BASE_HW_ISSUE_TTRX_3470,
352	402	BASE_HW_ISSUE_TTRX_3464,
353	403	BASE_HW_ISSUE_TTRX_3485,
	404	+ BASE_HW_ISSUE_TITANHW_2710,
	405	+ BASE_HW_ISSUE_GPU2022PRO_148,
354	406	BASE_HW_ISSUE_END
355	407	};
356	408
357		-static const enum base_hw_issue base_hw_issues_tTRx_r0p1[] = {
	409	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p1[] = {
358	410	BASE_HW_ISSUE_9435,
359	411	BASE_HW_ISSUE_TSIX_2033,
360	412	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -367,10 +419,12 @@
367	419	BASE_HW_ISSUE_TTRX_3470,
368	420	BASE_HW_ISSUE_TTRX_3464,
369	421	BASE_HW_ISSUE_TTRX_3485,
	422	+ BASE_HW_ISSUE_TITANHW_2710,
	423	+ BASE_HW_ISSUE_GPU2022PRO_148,
370	424	BASE_HW_ISSUE_END
371	425	};
372	426
373		-static const enum base_hw_issue base_hw_issues_tTRx_r0p2[] = {
	427	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p2[] = {
374	428	BASE_HW_ISSUE_9435,
375	429	BASE_HW_ISSUE_TSIX_2033,
376	430	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -382,10 +436,12 @@
382	436	BASE_HW_ISSUE_TTRX_3083,
383	437	BASE_HW_ISSUE_TTRX_3470,
384	438	BASE_HW_ISSUE_TTRX_3464,
	439	+ BASE_HW_ISSUE_TITANHW_2710,
	440	+ BASE_HW_ISSUE_GPU2022PRO_148,
385	441	BASE_HW_ISSUE_END
386	442	};
387	443
388		-static const enum base_hw_issue base_hw_issues_model_tTRx[] = {
	444	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTRx[] = {
389	445	BASE_HW_ISSUE_5736,
390	446	BASE_HW_ISSUE_9435,
391	447	BASE_HW_ISSUE_TSIX_2033,
..	..	@@ -394,10 +450,12 @@
394	450	BASE_HW_ISSUE_TTRX_3083,
395	451	BASE_HW_ISSUE_TTRX_3470,
396	452	BASE_HW_ISSUE_TTRX_3464,
	453	+ BASE_HW_ISSUE_TITANHW_2710,
	454	+ BASE_HW_ISSUE_GPU2022PRO_148,
397	455	BASE_HW_ISSUE_END
398	456	};
399	457
400		-static const enum base_hw_issue base_hw_issues_tNAx_r0p0[] = {
	458	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNAx_r0p0[] = {
401	459	BASE_HW_ISSUE_9435,
402	460	BASE_HW_ISSUE_TSIX_2033,
403	461	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -410,10 +468,12 @@
410	468	BASE_HW_ISSUE_TTRX_3470,
411	469	BASE_HW_ISSUE_TTRX_3464,
412	470	BASE_HW_ISSUE_TTRX_3485,
	471	+ BASE_HW_ISSUE_TITANHW_2710,
	472	+ BASE_HW_ISSUE_GPU2022PRO_148,
413	473	BASE_HW_ISSUE_END
414	474	};
415	475
416		-static const enum base_hw_issue base_hw_issues_tNAx_r0p1[] = {
	476	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNAx_r0p1[] = {
417	477	BASE_HW_ISSUE_9435,
418	478	BASE_HW_ISSUE_TSIX_2033,
419	479	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -425,10 +485,12 @@
425	485	BASE_HW_ISSUE_TTRX_3083,
426	486	BASE_HW_ISSUE_TTRX_3470,
427	487	BASE_HW_ISSUE_TTRX_3464,
	488	+ BASE_HW_ISSUE_TITANHW_2710,
	489	+ BASE_HW_ISSUE_GPU2022PRO_148,
428	490	BASE_HW_ISSUE_END
429	491	};
430	492
431		-static const enum base_hw_issue base_hw_issues_model_tNAx[] = {
	493	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tNAx[] = {
432	494	BASE_HW_ISSUE_5736,
433	495	BASE_HW_ISSUE_9435,
434	496	BASE_HW_ISSUE_TSIX_2033,
..	..	@@ -437,10 +499,12 @@
437	499	BASE_HW_ISSUE_TTRX_3083,
438	500	BASE_HW_ISSUE_TTRX_3470,
439	501	BASE_HW_ISSUE_TTRX_3464,
	502	+ BASE_HW_ISSUE_TITANHW_2710,
	503	+ BASE_HW_ISSUE_GPU2022PRO_148,
440	504	BASE_HW_ISSUE_END
441	505	};
442	506
443		-static const enum base_hw_issue base_hw_issues_tBEx_r0p0[] = {
	507	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r0p0[] = {
444	508	BASE_HW_ISSUE_9435,
445	509	BASE_HW_ISSUE_TSIX_2033,
446	510	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -451,10 +515,12 @@
451	515	BASE_HW_ISSUE_TTRX_3470,
452	516	BASE_HW_ISSUE_TTRX_3464,
453	517	BASE_HW_ISSUE_TTRX_3485,
	518	+ BASE_HW_ISSUE_TITANHW_2710,
	519	+ BASE_HW_ISSUE_GPU2022PRO_148,
454	520	BASE_HW_ISSUE_END
455	521	};
456	522
457		-static const enum base_hw_issue base_hw_issues_tBEx_r0p1[] = {
	523	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r0p1[] = {
458	524	BASE_HW_ISSUE_9435,
459	525	BASE_HW_ISSUE_TSIX_2033,
460	526	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -464,10 +530,12 @@
464	530	BASE_HW_ISSUE_TTRX_3083,
465	531	BASE_HW_ISSUE_TTRX_3470,
466	532	BASE_HW_ISSUE_TTRX_3464,
	533	+ BASE_HW_ISSUE_TITANHW_2710,
	534	+ BASE_HW_ISSUE_GPU2022PRO_148,
467	535	BASE_HW_ISSUE_END
468	536	};
469	537
470		-static const enum base_hw_issue base_hw_issues_tBEx_r1p0[] = {
	538	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r1p0[] = {
471	539	BASE_HW_ISSUE_9435,
472	540	BASE_HW_ISSUE_TSIX_2033,
473	541	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -477,10 +545,12 @@
477	545	BASE_HW_ISSUE_TTRX_3083,
478	546	BASE_HW_ISSUE_TTRX_3470,
479	547	BASE_HW_ISSUE_TTRX_3464,
	548	+ BASE_HW_ISSUE_TITANHW_2710,
	549	+ BASE_HW_ISSUE_GPU2022PRO_148,
480	550	BASE_HW_ISSUE_END
481	551	};
482	552
483		-static const enum base_hw_issue base_hw_issues_tBEx_r1p1[] = {
	553	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r1p1[] = {
484	554	BASE_HW_ISSUE_9435,
485	555	BASE_HW_ISSUE_TSIX_2033,
486	556	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -490,10 +560,12 @@
490	560	BASE_HW_ISSUE_TTRX_3083,
491	561	BASE_HW_ISSUE_TTRX_3470,
492	562	BASE_HW_ISSUE_TTRX_3464,
	563	+ BASE_HW_ISSUE_TITANHW_2710,
	564	+ BASE_HW_ISSUE_GPU2022PRO_148,
493	565	BASE_HW_ISSUE_END
494	566	};
495	567
496		-static const enum base_hw_issue base_hw_issues_model_tBEx[] = {
	568	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tBEx[] = {
497	569	BASE_HW_ISSUE_5736,
498	570	BASE_HW_ISSUE_9435,
499	571	BASE_HW_ISSUE_TSIX_2033,
..	..	@@ -502,10 +574,12 @@
502	574	BASE_HW_ISSUE_TTRX_3083,
503	575	BASE_HW_ISSUE_TTRX_3470,
504	576	BASE_HW_ISSUE_TTRX_3464,
	577	+ BASE_HW_ISSUE_TITANHW_2710,
	578	+ BASE_HW_ISSUE_GPU2022PRO_148,
505	579	BASE_HW_ISSUE_END
506	580	};
507	581
508		-static const enum base_hw_issue base_hw_issues_lBEx_r1p0[] = {
	582	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_lBEx_r1p0[] = {
509	583	BASE_HW_ISSUE_9435,
510	584	BASE_HW_ISSUE_TSIX_2033,
511	585	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -516,10 +590,12 @@
516	590	BASE_HW_ISSUE_TTRX_3470,
517	591	BASE_HW_ISSUE_TTRX_3464,
518	592	BASE_HW_ISSUE_TTRX_3485,
	593	+ BASE_HW_ISSUE_TITANHW_2710,
	594	+ BASE_HW_ISSUE_GPU2022PRO_148,
519	595	BASE_HW_ISSUE_END
520	596	};
521	597
522		-static const enum base_hw_issue base_hw_issues_lBEx_r1p1[] = {
	598	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_lBEx_r1p1[] = {
523	599	BASE_HW_ISSUE_9435,
524	600	BASE_HW_ISSUE_TSIX_2033,
525	601	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -529,10 +605,12 @@
529	605	BASE_HW_ISSUE_TTRX_3083,
530	606	BASE_HW_ISSUE_TTRX_3470,
531	607	BASE_HW_ISSUE_TTRX_3464,
	608	+ BASE_HW_ISSUE_TITANHW_2710,
	609	+ BASE_HW_ISSUE_GPU2022PRO_148,
532	610	BASE_HW_ISSUE_END
533	611	};
534	612
535		-static const enum base_hw_issue base_hw_issues_tBAx_r0p0[] = {
	613	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBAx_r0p0[] = {
536	614	BASE_HW_ISSUE_9435,
537	615	BASE_HW_ISSUE_TSIX_2033,
538	616	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -542,10 +620,12 @@
542	620	BASE_HW_ISSUE_TTRX_3083,
543	621	BASE_HW_ISSUE_TTRX_3470,
544	622	BASE_HW_ISSUE_TTRX_3464,
	623	+ BASE_HW_ISSUE_TITANHW_2710,
	624	+ BASE_HW_ISSUE_GPU2022PRO_148,
545	625	BASE_HW_ISSUE_END
546	626	};
547	627
548		-static const enum base_hw_issue base_hw_issues_tBAx_r1p0[] = {
	628	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBAx_r1p0[] = {
549	629	BASE_HW_ISSUE_9435,
550	630	BASE_HW_ISSUE_TSIX_2033,
551	631	BASE_HW_ISSUE_TTRX_1337,
..	..	@@ -555,10 +635,12 @@
555	635	BASE_HW_ISSUE_TTRX_3083,
556	636	BASE_HW_ISSUE_TTRX_3470,
557	637	BASE_HW_ISSUE_TTRX_3464,
	638	+ BASE_HW_ISSUE_TITANHW_2710,
	639	+ BASE_HW_ISSUE_GPU2022PRO_148,
558	640	BASE_HW_ISSUE_END
559	641	};
560	642
561		-static const enum base_hw_issue base_hw_issues_model_tBAx[] = {
	643	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tBAx[] = {
562	644	BASE_HW_ISSUE_5736,
563	645	BASE_HW_ISSUE_9435,
564	646	BASE_HW_ISSUE_TSIX_2033,
..	..	@@ -567,73 +649,185 @@
567	649	BASE_HW_ISSUE_TTRX_3083,
568	650	BASE_HW_ISSUE_TTRX_3470,
569	651	BASE_HW_ISSUE_TTRX_3464,
	652	+ BASE_HW_ISSUE_TITANHW_2710,
	653	+ BASE_HW_ISSUE_GPU2022PRO_148,
570	654	BASE_HW_ISSUE_END
571	655	};
572	656
573		-static const enum base_hw_issue base_hw_issues_tDUx_r0p0[] = {
574		- BASE_HW_ISSUE_9435,
575		- BASE_HW_ISSUE_TSIX_2033,
576		- BASE_HW_ISSUE_TTRX_1337,
577		- BASE_HW_ISSUE_TTRX_921,
578		- BASE_HW_ISSUE_TTRX_3414,
579		- BASE_HW_ISSUE_TTRX_3083,
580		- BASE_HW_ISSUE_END
581		-};
582		-
583		-static const enum base_hw_issue base_hw_issues_model_tDUx[] = {
584		- BASE_HW_ISSUE_5736,
585		- BASE_HW_ISSUE_9435,
586		- BASE_HW_ISSUE_TSIX_2033,
587		- BASE_HW_ISSUE_TTRX_1337,
588		- BASE_HW_ISSUE_TTRX_3414,
589		- BASE_HW_ISSUE_TTRX_3083,
590		- BASE_HW_ISSUE_END
591		-};
592		-
593		-static const enum base_hw_issue base_hw_issues_tODx_r0p0[] = {
594		- BASE_HW_ISSUE_9435,
	657	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tODx_r0p0[] = {
595	658	BASE_HW_ISSUE_TSIX_2033,
596	659	BASE_HW_ISSUE_TTRX_1337,
597	660	BASE_HW_ISSUE_GPU2019_3212,
	661	+ BASE_HW_ISSUE_GPU2019_3878,
	662	+ BASE_HW_ISSUE_GPU2019_3901,
	663	+ BASE_HW_ISSUE_TITANHW_2710,
	664	+ BASE_HW_ISSUE_GPU2022PRO_148,
598	665	BASE_HW_ISSUE_END
599	666	};
600	667
601		-static const enum base_hw_issue base_hw_issues_model_tODx[] = {
602		- BASE_HW_ISSUE_5736,
603		- BASE_HW_ISSUE_9435,
	668	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tODx[] = {
604	669	BASE_HW_ISSUE_TSIX_2033,
605	670	BASE_HW_ISSUE_TTRX_1337,
606	671	BASE_HW_ISSUE_GPU2019_3212,
	672	+ BASE_HW_ISSUE_GPU2019_3878,
	673	+ BASE_HW_ISSUE_GPU2019_3901,
	674	+ BASE_HW_ISSUE_TITANHW_2710,
	675	+ BASE_HW_ISSUE_GPU2022PRO_148,
607	676	BASE_HW_ISSUE_END
608	677	};
609	678
610		-static const enum base_hw_issue base_hw_issues_tGRx_r0p0[] = {
611		- BASE_HW_ISSUE_9435,
	679	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGRx_r0p0[] = {
612	680	BASE_HW_ISSUE_TSIX_2033,
613	681	BASE_HW_ISSUE_TTRX_1337,
	682	+ BASE_HW_ISSUE_GPU2019_3878,
	683	+ BASE_HW_ISSUE_GPU2019_3901,
	684	+ BASE_HW_ISSUE_TITANHW_2710,
	685	+ BASE_HW_ISSUE_GPU2022PRO_148,
614	686	BASE_HW_ISSUE_END
615	687	};
616	688
617		-static const enum base_hw_issue base_hw_issues_model_tGRx[] = {
618		- BASE_HW_ISSUE_5736,
619		- BASE_HW_ISSUE_9435,
	689	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tGRx[] = {
620	690	BASE_HW_ISSUE_TSIX_2033,
621	691	BASE_HW_ISSUE_TTRX_1337,
	692	+ BASE_HW_ISSUE_GPU2019_3878,
	693	+ BASE_HW_ISSUE_GPU2019_3901,
	694	+ BASE_HW_ISSUE_TITANHW_2710,
	695	+ BASE_HW_ISSUE_GPU2022PRO_148,
622	696	BASE_HW_ISSUE_END
623	697	};
624	698
625		-static const enum base_hw_issue base_hw_issues_tVAx_r0p0[] = {
626		- BASE_HW_ISSUE_9435,
	699	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tVAx_r0p0[] = {
627	700	BASE_HW_ISSUE_TSIX_2033,
628	701	BASE_HW_ISSUE_TTRX_1337,
	702	+ BASE_HW_ISSUE_GPU2019_3878,
	703	+ BASE_HW_ISSUE_GPU2019_3901,
	704	+ BASE_HW_ISSUE_TITANHW_2710,
	705	+ BASE_HW_ISSUE_GPU2022PRO_148,
629	706	BASE_HW_ISSUE_END
630	707	};
631	708
632		-static const enum base_hw_issue base_hw_issues_model_tVAx[] = {
633		- BASE_HW_ISSUE_5736,
634		- BASE_HW_ISSUE_9435,
	709	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tVAx[] = {
635	710	BASE_HW_ISSUE_TSIX_2033,
636	711	BASE_HW_ISSUE_TTRX_1337,
	712	+ BASE_HW_ISSUE_GPU2019_3878,
	713	+ BASE_HW_ISSUE_GPU2019_3901,
	714	+ BASE_HW_ISSUE_TITANHW_2710,
	715	+ BASE_HW_ISSUE_GPU2022PRO_148,
	716	+ BASE_HW_ISSUE_END
	717	+};
	718	+
	719	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r0p0[] = {
	720	+ BASE_HW_ISSUE_TSIX_2033,
	721	+ BASE_HW_ISSUE_TTRX_1337,
	722	+ BASE_HW_ISSUE_TURSEHW_1997,
	723	+ BASE_HW_ISSUE_GPU2019_3878,
	724	+ BASE_HW_ISSUE_TURSEHW_2716,
	725	+ BASE_HW_ISSUE_GPU2019_3901,
	726	+ BASE_HW_ISSUE_GPU2021PRO_290,
	727	+ BASE_HW_ISSUE_TITANHW_2710,
	728	+ BASE_HW_ISSUE_TITANHW_2679,
	729	+ BASE_HW_ISSUE_GPU2022PRO_148,
	730	+ BASE_HW_ISSUE_END
	731	+};
	732	+
	733	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r0p1[] = {
	734	+ BASE_HW_ISSUE_TSIX_2033,
	735	+ BASE_HW_ISSUE_TTRX_1337,
	736	+ BASE_HW_ISSUE_TURSEHW_1997,
	737	+ BASE_HW_ISSUE_GPU2019_3878,
	738	+ BASE_HW_ISSUE_TURSEHW_2716,
	739	+ BASE_HW_ISSUE_GPU2019_3901,
	740	+ BASE_HW_ISSUE_GPU2021PRO_290,
	741	+ BASE_HW_ISSUE_TITANHW_2710,
	742	+ BASE_HW_ISSUE_TITANHW_2679,
	743	+ BASE_HW_ISSUE_GPU2022PRO_148,
	744	+ BASE_HW_ISSUE_END
	745	+};
	746	+
	747	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTUx[] = {
	748	+ BASE_HW_ISSUE_TSIX_2033,
	749	+ BASE_HW_ISSUE_TTRX_1337,
	750	+ BASE_HW_ISSUE_GPU2019_3878,
	751	+ BASE_HW_ISSUE_TURSEHW_2716,
	752	+ BASE_HW_ISSUE_GPU2019_3901,
	753	+ BASE_HW_ISSUE_GPU2021PRO_290,
	754	+ BASE_HW_ISSUE_TITANHW_2710,
	755	+ BASE_HW_ISSUE_TITANHW_2679,
	756	+ BASE_HW_ISSUE_GPU2022PRO_148,
	757	+ BASE_HW_ISSUE_END
	758	+};
	759	+
	760	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p0[] = {
	761	+ BASE_HW_ISSUE_TSIX_2033,
	762	+ BASE_HW_ISSUE_TTRX_1337,
	763	+ BASE_HW_ISSUE_GPU2019_3878,
	764	+ BASE_HW_ISSUE_TURSEHW_2716,
	765	+ BASE_HW_ISSUE_GPU2019_3901,
	766	+ BASE_HW_ISSUE_GPU2021PRO_290,
	767	+ BASE_HW_ISSUE_TITANHW_2710,
	768	+ BASE_HW_ISSUE_TITANHW_2679,
	769	+ BASE_HW_ISSUE_GPU2022PRO_148,
	770	+ BASE_HW_ISSUE_END
	771	+};
	772	+
	773	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p1[] = {
	774	+ BASE_HW_ISSUE_TSIX_2033,
	775	+ BASE_HW_ISSUE_TTRX_1337,
	776	+ BASE_HW_ISSUE_GPU2019_3878,
	777	+ BASE_HW_ISSUE_TURSEHW_2716,
	778	+ BASE_HW_ISSUE_GPU2019_3901,
	779	+ BASE_HW_ISSUE_GPU2021PRO_290,
	780	+ BASE_HW_ISSUE_TITANHW_2710,
	781	+ BASE_HW_ISSUE_TITANHW_2679,
	782	+ BASE_HW_ISSUE_GPU2022PRO_148,
	783	+ BASE_HW_ISSUE_END
	784	+};
	785	+
	786	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p2[] = {
	787	+ BASE_HW_ISSUE_TSIX_2033,
	788	+ BASE_HW_ISSUE_TTRX_1337,
	789	+ BASE_HW_ISSUE_GPU2019_3878,
	790	+ BASE_HW_ISSUE_TURSEHW_2716,
	791	+ BASE_HW_ISSUE_GPU2019_3901,
	792	+ BASE_HW_ISSUE_GPU2021PRO_290,
	793	+ BASE_HW_ISSUE_TITANHW_2710,
	794	+ BASE_HW_ISSUE_TITANHW_2679,
	795	+ BASE_HW_ISSUE_GPU2022PRO_148,
	796	+ BASE_HW_ISSUE_END
	797	+};
	798	+
	799	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p3[] = {
	800	+ BASE_HW_ISSUE_TSIX_2033,
	801	+ BASE_HW_ISSUE_TTRX_1337,
	802	+ BASE_HW_ISSUE_GPU2019_3878,
	803	+ BASE_HW_ISSUE_TURSEHW_2716,
	804	+ BASE_HW_ISSUE_GPU2019_3901,
	805	+ BASE_HW_ISSUE_GPU2021PRO_290,
	806	+ BASE_HW_ISSUE_TITANHW_2710,
	807	+ BASE_HW_ISSUE_TITANHW_2679,
	808	+ BASE_HW_ISSUE_GPU2022PRO_148,
	809	+ BASE_HW_ISSUE_END
	810	+};
	811	+
	812	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTIx[] = {
	813	+ BASE_HW_ISSUE_TSIX_2033,
	814	+ BASE_HW_ISSUE_TTRX_1337,
	815	+ BASE_HW_ISSUE_TURSEHW_2716,
	816	+ BASE_HW_ISSUE_GPU2021PRO_290,
	817	+ BASE_HW_ISSUE_TITANHW_2710,
	818	+ BASE_HW_ISSUE_TITANHW_2679,
	819	+ BASE_HW_ISSUE_GPU2022PRO_148,
	820	+ BASE_HW_ISSUE_END
	821	+};
	822	+
	823	+__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTIx_r0p0[] = {
	824	+ BASE_HW_ISSUE_TSIX_2033,
	825	+ BASE_HW_ISSUE_TTRX_1337,
	826	+ BASE_HW_ISSUE_TURSEHW_2716,
	827	+ BASE_HW_ISSUE_GPU2021PRO_290,
	828	+ BASE_HW_ISSUE_TITANHW_2710,
	829	+ BASE_HW_ISSUE_TITANHW_2679,
	830	+ BASE_HW_ISSUE_GPU2022PRO_148,
637	831	BASE_HW_ISSUE_END
638	832	};
639	833