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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/firmware/qcom_scm.h
....@@ -1,70 +1,124 @@
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-/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
113  */
124 #ifndef __QCOM_SCM_INT_H
135 #define __QCOM_SCM_INT_H
146 
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-#define QCOM_SCM_SVC_BOOT		0x1
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-#define QCOM_SCM_BOOT_ADDR		0x1
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-#define QCOM_SCM_SET_DLOAD_MODE		0x10
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-#define QCOM_SCM_BOOT_ADDR_MC		0x11
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-#define QCOM_SCM_SET_REMOTE_STATE	0xa
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-extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
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-extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
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+enum qcom_scm_convention {
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+	SMC_CONVENTION_UNKNOWN,
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+	SMC_CONVENTION_LEGACY,
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+	SMC_CONVENTION_ARM_32,
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+	SMC_CONVENTION_ARM_64,
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+};
2213 
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-#define QCOM_SCM_FLAG_HLOS		0x01
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-#define QCOM_SCM_FLAG_COLDBOOT_MC	0x02
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-#define QCOM_SCM_FLAG_WARMBOOT_MC	0x04
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-extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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-		const cpumask_t *cpus);
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-extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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+extern enum qcom_scm_convention qcom_scm_convention;
2915 
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-#define QCOM_SCM_CMD_TERMINATE_PC	0x2
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+#define MAX_QCOM_SCM_ARGS 10
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+#define MAX_QCOM_SCM_RETS 3
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+
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+enum qcom_scm_arg_types {
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+	QCOM_SCM_VAL,
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+	QCOM_SCM_RO,
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+	QCOM_SCM_RW,
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+	QCOM_SCM_BUFVAL,
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+};
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+
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+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
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+			   (((a) & 0x3) << 4) | \
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+			   (((b) & 0x3) << 6) | \
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+			   (((c) & 0x3) << 8) | \
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+			   (((d) & 0x3) << 10) | \
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+			   (((e) & 0x3) << 12) | \
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+			   (((f) & 0x3) << 14) | \
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+			   (((g) & 0x3) << 16) | \
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+			   (((h) & 0x3) << 18) | \
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+			   (((i) & 0x3) << 20) | \
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+			   (((j) & 0x3) << 22) | \
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+			   ((num) & 0xf))
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+
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+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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+
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+
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+/**
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+ * struct qcom_scm_desc
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+ * @arginfo:	Metadata describing the arguments in args[]
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+ * @args:	The array of arguments for the secure syscall
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+ */
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+struct qcom_scm_desc {
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+	u32 svc;
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+	u32 cmd;
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+	u32 arginfo;
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+	u64 args[MAX_QCOM_SCM_ARGS];
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+	u32 owner;
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+};
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+
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+/**
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+ * struct qcom_scm_res
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+ * @result:	The values returned by the secure syscall
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+ */
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+struct qcom_scm_res {
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+	u64 result[MAX_QCOM_SCM_RETS];
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+};
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+
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+#define SCM_SMC_FNID(s, c)	((((s) & 0xFF) << 8) | ((c) & 0xFF))
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+extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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+			  enum qcom_scm_convention qcom_convention,
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+			  struct qcom_scm_res *res, bool atomic);
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+#define scm_smc_call(dev, desc, res, atomic) \
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+	__scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
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+
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+#define SCM_LEGACY_FNID(s, c)	(((s) << 10) | ((c) & 0x3ff))
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+extern int scm_legacy_call_atomic(struct device *dev,
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+				  const struct qcom_scm_desc *desc,
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+				  struct qcom_scm_res *res);
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+extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
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+			   struct qcom_scm_res *res);
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+
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+#define QCOM_SCM_SVC_BOOT		0x01
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+#define QCOM_SCM_BOOT_SET_ADDR		0x01
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+#define QCOM_SCM_BOOT_TERMINATE_PC	0x02
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+#define QCOM_SCM_BOOT_SET_DLOAD_MODE	0x10
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+#define QCOM_SCM_BOOT_SET_REMOTE_STATE	0x0a
3182 #define QCOM_SCM_FLUSH_FLAG_MASK	0x3
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-#define QCOM_SCM_CMD_CORE_HOTPLUGGED	0x10
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-extern void __qcom_scm_cpu_power_down(u32 flags);
3483 
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-#define QCOM_SCM_SVC_IO			0x5
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-#define QCOM_SCM_IO_READ		0x1
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-#define QCOM_SCM_IO_WRITE		0x2
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-extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
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-extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
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+#define QCOM_SCM_SVC_PIL		0x02
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+#define QCOM_SCM_PIL_PAS_INIT_IMAGE	0x01
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+#define QCOM_SCM_PIL_PAS_MEM_SETUP	0x02
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+#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET	0x05
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+#define QCOM_SCM_PIL_PAS_SHUTDOWN	0x06
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+#define QCOM_SCM_PIL_PAS_IS_SUPPORTED	0x07
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+#define QCOM_SCM_PIL_PAS_MSS_RESET	0x0a
4091 
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-#define QCOM_SCM_SVC_INFO		0x6
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-#define QCOM_IS_CALL_AVAIL_CMD		0x1
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-extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
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-		u32 cmd_id);
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+#define QCOM_SCM_SVC_IO			0x05
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+#define QCOM_SCM_IO_READ		0x01
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+#define QCOM_SCM_IO_WRITE		0x02
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+
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+#define QCOM_SCM_SVC_INFO		0x06
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+#define QCOM_SCM_INFO_IS_CALL_AVAIL	0x01
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+
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+#define QCOM_SCM_SVC_MP				0x0c
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+#define QCOM_SCM_MP_RESTORE_SEC_CFG		0x02
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+#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE	0x03
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+#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT	0x04
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+#define QCOM_SCM_MP_VIDEO_VAR			0x08
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+#define QCOM_SCM_MP_ASSIGN			0x16
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+
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+#define QCOM_SCM_SVC_OCMEM		0x0f
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+#define QCOM_SCM_OCMEM_LOCK_CMD		0x01
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+#define QCOM_SCM_OCMEM_UNLOCK_CMD	0x02
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+
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+#define QCOM_SCM_SVC_ES			0x10	/* Enterprise Security */
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+#define QCOM_SCM_ES_INVALIDATE_ICE_KEY	0x03
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+#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY	0x04
45113 
46114 #define QCOM_SCM_SVC_HDCP		0x11
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-#define QCOM_SCM_CMD_HDCP		0x01
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-extern int __qcom_scm_hdcp_req(struct device *dev,
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-		struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
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+#define QCOM_SCM_HDCP_INVOKE		0x01
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+
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+#define QCOM_SCM_SVC_SMMU_PROGRAM		0x15
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+#define QCOM_SCM_SMMU_CONFIG_ERRATA1		0x03
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+#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL	0x02
50120 
51121 extern void __qcom_scm_init(void);
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-
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-#define QCOM_SCM_SVC_PIL		0x2
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-#define QCOM_SCM_PAS_INIT_IMAGE_CMD	0x1
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-#define QCOM_SCM_PAS_MEM_SETUP_CMD	0x2
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-#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD	0x5
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-#define QCOM_SCM_PAS_SHUTDOWN_CMD	0x6
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-#define QCOM_SCM_PAS_IS_SUPPORTED_CMD	0x7
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-#define QCOM_SCM_PAS_MSS_RESET		0xa
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-extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
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-extern int  __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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-		dma_addr_t metadata_phys);
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-extern int  __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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-		phys_addr_t addr, phys_addr_t size);
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-extern int  __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
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-extern int  __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
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-extern int  __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
68122 
69123 /* common error codes */
70124 #define QCOM_SCM_V2_EBUSY	-12
....@@ -92,21 +146,5 @@
92146 	}
93147 	return -EINVAL;
94148 }
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-
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-#define QCOM_SCM_SVC_MP			0xc
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-#define QCOM_SCM_RESTORE_SEC_CFG	2
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-extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
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-				      u32 spare);
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-#define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE	3
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-#define QCOM_SCM_IOMMU_SECURE_PTBL_INIT	4
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-extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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-					     size_t *size);
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-extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
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-					     u32 size, u32 spare);
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-#define QCOM_MEM_PROT_ASSIGN_ID	0x16
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-extern int  __qcom_scm_assign_mem(struct device *dev,
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-				  phys_addr_t mem_region, size_t mem_sz,
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-				  phys_addr_t src, size_t src_sz,
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-				  phys_addr_t dest, size_t dest_sz);
111149 
112150 #endif