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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/crypto/cavium/nitrox/nitrox_csr.h
....@@ -7,8 +7,15 @@
77 
88 /* EMU clusters */
99 #define NR_CLUSTERS		4
10
+/* Maximum cores per cluster,
11
+ * varies based on partname
12
+ */
1013 #define AE_CORES_PER_CLUSTER	20
1114 #define SE_CORES_PER_CLUSTER	16
15
+
16
+#define AE_MAX_CORES	(AE_CORES_PER_CLUSTER * NR_CLUSTERS)
17
+#define SE_MAX_CORES	(SE_CORES_PER_CLUSTER * NR_CLUSTERS)
18
+#define ZIP_MAX_CORES	5
1219 
1320 /* BIST registers */
1421 #define EMU_BIST_STATUSX(_i)	(0x1402700 + ((_i) * 0x40000))
....@@ -33,9 +40,77 @@
3340 #define EMU_FUSE_MAPX(_i)	(0x1402708 + ((_i) * 0x40000))
3441 
3542 /* UCD registers */
43
+#define UCD_SE_EID_UCODE_BLOCK_NUMX(_i)	(0x12C0000 + ((_i) * 0x1000))
44
+#define UCD_AE_EID_UCODE_BLOCK_NUMX(_i)	(0x12C0008 + ((_i) * 0x800))
3645 #define UCD_UCODE_LOAD_BLOCK_NUM	0x12C0010
3746 #define UCD_UCODE_LOAD_IDX_DATAX(_i)	(0x12C0018 + ((_i) * 0x20))
38
-#define UCD_SE_EID_UCODE_BLOCK_NUMX(_i)	(0x12C0000 + ((_i) * 0x1000))
47
+#define UCD_SE_CNTX(_i)			(0x12C0040 + ((_i) * 0x1000))
48
+#define UCD_AE_CNTX(_i)			(0x12C0048 + ((_i) * 0x800))
49
+
50
+/* AQM registers */
51
+#define AQM_CTL                         0x1300000
52
+#define AQM_INT                         0x1300008
53
+#define AQM_DBELL_OVF_LO                0x1300010
54
+#define AQM_DBELL_OVF_HI                0x1300018
55
+#define AQM_DBELL_OVF_LO_W1S            0x1300020
56
+#define AQM_DBELL_OVF_LO_ENA_W1C        0x1300028
57
+#define AQM_DBELL_OVF_LO_ENA_W1S        0x1300030
58
+#define AQM_DBELL_OVF_HI_W1S            0x1300038
59
+#define AQM_DBELL_OVF_HI_ENA_W1C        0x1300040
60
+#define AQM_DBELL_OVF_HI_ENA_W1S        0x1300048
61
+#define AQM_DMA_RD_ERR_LO               0x1300050
62
+#define AQM_DMA_RD_ERR_HI               0x1300058
63
+#define AQM_DMA_RD_ERR_LO_W1S           0x1300060
64
+#define AQM_DMA_RD_ERR_LO_ENA_W1C       0x1300068
65
+#define AQM_DMA_RD_ERR_LO_ENA_W1S       0x1300070
66
+#define AQM_DMA_RD_ERR_HI_W1S           0x1300078
67
+#define AQM_DMA_RD_ERR_HI_ENA_W1C       0x1300080
68
+#define AQM_DMA_RD_ERR_HI_ENA_W1S       0x1300088
69
+#define AQM_EXEC_NA_LO                  0x1300090
70
+#define AQM_EXEC_NA_HI                  0x1300098
71
+#define AQM_EXEC_NA_LO_W1S              0x13000A0
72
+#define AQM_EXEC_NA_LO_ENA_W1C          0x13000A8
73
+#define AQM_EXEC_NA_LO_ENA_W1S          0x13000B0
74
+#define AQM_EXEC_NA_HI_W1S              0x13000B8
75
+#define AQM_EXEC_NA_HI_ENA_W1C          0x13000C0
76
+#define AQM_EXEC_NA_HI_ENA_W1S          0x13000C8
77
+#define AQM_EXEC_ERR_LO                 0x13000D0
78
+#define AQM_EXEC_ERR_HI                 0x13000D8
79
+#define AQM_EXEC_ERR_LO_W1S             0x13000E0
80
+#define AQM_EXEC_ERR_LO_ENA_W1C         0x13000E8
81
+#define AQM_EXEC_ERR_LO_ENA_W1S         0x13000F0
82
+#define AQM_EXEC_ERR_HI_W1S             0x13000F8
83
+#define AQM_EXEC_ERR_HI_ENA_W1C         0x1300100
84
+#define AQM_EXEC_ERR_HI_ENA_W1S         0x1300108
85
+#define AQM_ECC_INT                     0x1300110
86
+#define AQM_ECC_INT_W1S                 0x1300118
87
+#define AQM_ECC_INT_ENA_W1C             0x1300120
88
+#define AQM_ECC_INT_ENA_W1S             0x1300128
89
+#define AQM_ECC_CTL                     0x1300130
90
+#define AQM_BIST_STATUS                 0x1300138
91
+#define AQM_CMD_INF_THRX(x)             (0x1300400 + ((x) * 0x8))
92
+#define AQM_CMD_INFX(x)                 (0x1300800 + ((x) * 0x8))
93
+#define AQM_GRP_EXECMSK_LOX(x)          (0x1300C00 + ((x) * 0x10))
94
+#define AQM_GRP_EXECMSK_HIX(x)          (0x1300C08 + ((x) * 0x10))
95
+#define AQM_ACTIVITY_STAT_LO            0x1300C80
96
+#define AQM_ACTIVITY_STAT_HI            0x1300C88
97
+#define AQM_Q_CMD_PROCX(x)              (0x1301000 + ((x) * 0x8))
98
+#define AQM_PERF_CTL_LO                 0x1301400
99
+#define AQM_PERF_CTL_HI                 0x1301408
100
+#define AQM_PERF_CNT                    0x1301410
101
+
102
+#define AQMQ_DRBLX(x)                   (0x20000 + ((x) * 0x40000))
103
+#define AQMQ_QSZX(x)                    (0x20008 + ((x) * 0x40000))
104
+#define AQMQ_BADRX(x)                   (0x20010 + ((x) * 0x40000))
105
+#define AQMQ_NXT_CMDX(x)                (0x20018 + ((x) * 0x40000))
106
+#define AQMQ_CMD_CNTX(x)                (0x20020 + ((x) * 0x40000))
107
+#define AQMQ_CMP_THRX(x)                (0x20028 + ((x) * 0x40000))
108
+#define AQMQ_CMP_CNTX(x)                (0x20030 + ((x) * 0x40000))
109
+#define AQMQ_TIM_LDX(x)                 (0x20038 + ((x) * 0x40000))
110
+#define AQMQ_TIMERX(x)                  (0x20040 + ((x) * 0x40000))
111
+#define AQMQ_ENX(x)                     (0x20048 + ((x) * 0x40000))
112
+#define AQMQ_ACTIVITY_STATX(x)          (0x20050 + ((x) * 0x40000))
113
+#define AQM_VF_CMP_STATX(x)             (0x28000 + ((x) * 0x40000))
39114 
40115 /* NPS core registers */
41116 #define NPS_CORE_GBL_VFCFG	0x1000000
....@@ -47,7 +122,13 @@
47122 #define NPS_STATS_PKT_DMA_WR_CNT	0x1000190
48123 
49124 /* NPS packet registers */
50
-#define NPS_PKT_INT				0x1040018
125
+#define NPS_PKT_INT			0x1040018
126
+#define NPS_PKT_MBOX_INT_LO		0x1040020
127
+#define NPS_PKT_MBOX_INT_LO_ENA_W1C	0x1040030
128
+#define NPS_PKT_MBOX_INT_LO_ENA_W1S	0x1040038
129
+#define NPS_PKT_MBOX_INT_HI		0x1040040
130
+#define NPS_PKT_MBOX_INT_HI_ENA_W1C	0x1040050
131
+#define NPS_PKT_MBOX_INT_HI_ENA_W1S	0x1040058
51132 #define NPS_PKT_IN_RERR_HI		0x1040108
52133 #define NPS_PKT_IN_RERR_HI_ENA_W1S	0x1040120
53134 #define NPS_PKT_IN_RERR_LO		0x1040128
....@@ -67,6 +148,10 @@
67148 #define NPS_PKT_SLC_RERR_LO_ENA_W1S	0x1040240
68149 #define NPS_PKT_SLC_ERR_TYPE		0x1040248
69150 #define NPS_PKT_SLC_ERR_TYPE_ENA_W1S	0x1040260
151
+/* Mailbox PF->VF PF Accessible Data registers */
152
+#define NPS_PKT_MBOX_PF_VF_PFDATAX(_i)	(0x1040800 + ((_i) * 0x8))
153
+#define NPS_PKT_MBOX_VF_PF_PFDATAX(_i)	(0x1040C00 + ((_i) * 0x8))
154
+
70155 #define NPS_PKT_SLC_CTLX(_i)		(0x10000 + ((_i) * 0x40000))
71156 #define NPS_PKT_SLC_CNTSX(_i)		(0x10008 + ((_i) * 0x40000))
72157 #define NPS_PKT_SLC_INT_LEVELSX(_i)	(0x10010 + ((_i) * 0x40000))
....@@ -111,8 +196,176 @@
111196 #define LBC_ELM_VF65_128_INT		0x120C000
112197 #define LBC_ELM_VF65_128_INT_ENA_W1S	0x120F000
113198 
199
+#define RST_BOOT	0x10C1600
200
+#define FUS_DAT1	0x10C1408
201
+
114202 /* PEM registers */
115203 #define PEM0_INT 0x1080428
204
+
205
+/**
206
+ * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers
207
+ * @ucode_len: Ucode length identifier 32KB or 64KB
208
+ * @ucode_blk: Ucode Block Number
209
+ */
210
+union ucd_core_eid_ucode_block_num {
211
+	u64 value;
212
+	struct {
213
+#if (defined(__BIG_ENDIAN_BITFIELD))
214
+		u64 raz_4_63 : 60;
215
+		u64 ucode_len : 1;
216
+		u64 ucode_blk : 3;
217
+#else
218
+		u64 ucode_blk : 3;
219
+		u64 ucode_len : 1;
220
+		u64 raz_4_63 : 60;
221
+#endif
222
+	};
223
+};
224
+
225
+/**
226
+ * struct aqm_grp_execmsk_lo - Available AE engines for the group
227
+ * @exec_0_to_39: AE engines 0 to 39 status
228
+ */
229
+union aqm_grp_execmsk_lo {
230
+	u64 value;
231
+	struct {
232
+#if (defined(__BIG_ENDIAN_BITFIELD))
233
+		u64 raz_40_63 : 24;
234
+		u64 exec_0_to_39 : 40;
235
+#else
236
+		u64 exec_0_to_39 : 40;
237
+		u64 raz_40_63 : 24;
238
+#endif
239
+	};
240
+};
241
+
242
+/**
243
+ * struct aqm_grp_execmsk_hi - Available AE engines for the group
244
+ * @exec_40_to_79: AE engines 40 to 79 status
245
+ */
246
+union aqm_grp_execmsk_hi {
247
+	u64 value;
248
+	struct {
249
+#if (defined(__BIG_ENDIAN_BITFIELD))
250
+		u64 raz_40_63 : 24;
251
+		u64 exec_40_to_79 : 40;
252
+#else
253
+		u64 exec_40_to_79 : 40;
254
+		u64 raz_40_63 : 24;
255
+#endif
256
+	};
257
+};
258
+
259
+/**
260
+ * struct aqmq_drbl - AQM Queue Doorbell Counter Registers
261
+ * @dbell_count: Doorbell Counter
262
+ */
263
+union aqmq_drbl {
264
+	u64 value;
265
+	struct {
266
+#if (defined(__BIG_ENDIAN_BITFIELD))
267
+		u64 raz_32_63 : 32;
268
+		u64 dbell_count : 32;
269
+#else
270
+		u64 dbell_count : 32;
271
+		u64 raz_32_63 : 32;
272
+#endif
273
+	};
274
+};
275
+
276
+/**
277
+ * struct aqmq_qsz - AQM Queue Host Queue Size Registers
278
+ * @host_queue_size: Size, in numbers of 'aqmq_command_s' command
279
+ * of the Host Ring.
280
+ */
281
+union aqmq_qsz {
282
+	u64 value;
283
+	struct {
284
+#if (defined(__BIG_ENDIAN_BITFIELD))
285
+		u64 raz_32_63 : 32;
286
+		u64 host_queue_size : 32;
287
+#else
288
+		u64 host_queue_size : 32;
289
+		u64 raz_32_63 : 32;
290
+#endif
291
+	};
292
+};
293
+
294
+/**
295
+ * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers
296
+ * @commands_completed_threshold: Count of 'aqmq_command_s' commands executed
297
+ * by AE engines for which completion interrupt is asserted.
298
+ */
299
+union aqmq_cmp_thr {
300
+	u64 value;
301
+	struct {
302
+#if (defined(__BIG_ENDIAN_BITFIELD))
303
+		u64 raz_32_63 : 32;
304
+		u64 commands_completed_threshold : 32;
305
+#else
306
+		u64 commands_completed_threshold : 32;
307
+		u64 raz_32_63 : 32;
308
+#endif
309
+	};
310
+};
311
+
312
+/**
313
+ * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers
314
+ * @resend: Bit to request completion interrupt Resend.
315
+ * @completion_status: Command completion status of the ring.
316
+ * @commands_completed_count: Count of 'aqmq_command_s' commands executed by
317
+ * AE engines.
318
+ */
319
+union aqmq_cmp_cnt {
320
+	u64 value;
321
+	struct {
322
+#if (defined(__BIG_ENDIAN_BITFIELD))
323
+		u64 raz_34_63 : 30;
324
+		u64 resend : 1;
325
+		u64 completion_status : 1;
326
+		u64 commands_completed_count : 32;
327
+#else
328
+		u64 commands_completed_count : 32;
329
+		u64 completion_status : 1;
330
+		u64 resend : 1;
331
+		u64 raz_34_63 : 30;
332
+#endif
333
+	};
334
+};
335
+
336
+/**
337
+ * struct aqmq_en - AQM Queue Enable Registers
338
+ * @queue_status: 1 = AQMQ is enabled, 0 = AQMQ is disabled
339
+ */
340
+union aqmq_en {
341
+	u64 value;
342
+	struct {
343
+#if (defined(__BIG_ENDIAN_BITFIELD))
344
+		u64 raz_1_63 : 63;
345
+		u64 queue_enable : 1;
346
+#else
347
+		u64 queue_enable : 1;
348
+		u64 raz_1_63 : 63;
349
+#endif
350
+	};
351
+};
352
+
353
+/**
354
+ * struct aqmq_activity_stat - AQM Queue Activity Status Registers
355
+ * @queue_active: 1 = AQMQ is active, 0 = AQMQ is quiescent
356
+ */
357
+union aqmq_activity_stat {
358
+	u64 value;
359
+	struct {
360
+#if (defined(__BIG_ENDIAN_BITFIELD))
361
+		u64 raz_1_63 : 63;
362
+		u64 queue_active : 1;
363
+#else
364
+		u64 queue_active : 1;
365
+		u64 raz_1_63 : 63;
366
+#endif
367
+	};
368
+};
116369 
117370 /**
118371  * struct emu_fuse_map - EMU Fuse Map Registers
....@@ -1082,4 +1335,105 @@
10821335 	} s;
10831336 };
10841337 
1338
+/**
1339
+ * struct rst_boot: RST Boot Register
1340
+ * @jtcsrdis: when set, internal CSR access via JTAG TAP controller
1341
+ *   is disabled
1342
+ * @jt_tst_mode: JTAG test mode
1343
+ * @io_supply: I/O power supply setting based on IO_VDD_SELECT pin:
1344
+ *    0x1 = 1.8V
1345
+ *    0x2 = 2.5V
1346
+ *    0x4 = 3.3V
1347
+ *    All other values are reserved
1348
+ * @pnr_mul: clock multiplier
1349
+ * @lboot: last boot cause mask, resets only with PLL_DC_OK
1350
+ * @rboot: determines whether core 0 remains in reset after
1351
+ *    chip cold or warm or soft reset
1352
+ * @rboot_pin: read only access to REMOTE_BOOT pin
1353
+ */
1354
+union rst_boot {
1355
+	u64 value;
1356
+	struct {
1357
+#if (defined(__BIG_ENDIAN_BITFIELD))
1358
+		u64 raz_63 : 1;
1359
+		u64 jtcsrdis : 1;
1360
+		u64 raz_59_61 : 3;
1361
+		u64 jt_tst_mode : 1;
1362
+		u64 raz_40_57 : 18;
1363
+		u64 io_supply : 3;
1364
+		u64 raz_30_36 : 7;
1365
+		u64 pnr_mul : 6;
1366
+		u64 raz_12_23 : 12;
1367
+		u64 lboot : 10;
1368
+		u64 rboot : 1;
1369
+		u64 rboot_pin : 1;
1370
+#else
1371
+		u64 rboot_pin : 1;
1372
+		u64 rboot : 1;
1373
+		u64 lboot : 10;
1374
+		u64 raz_12_23 : 12;
1375
+		u64 pnr_mul : 6;
1376
+		u64 raz_30_36 : 7;
1377
+		u64 io_supply : 3;
1378
+		u64 raz_40_57 : 18;
1379
+		u64 jt_tst_mode : 1;
1380
+		u64 raz_59_61 : 3;
1381
+		u64 jtcsrdis : 1;
1382
+		u64 raz_63 : 1;
1383
+#endif
1384
+	};
1385
+};
1386
+
1387
+/**
1388
+ * struct fus_dat1: Fuse Data 1 Register
1389
+ * @pll_mul: main clock PLL multiplier hardware limit
1390
+ * @pll_half_dis: main clock PLL control
1391
+ * @efus_lck: efuse lockdown
1392
+ * @zip_info: ZIP information
1393
+ * @bar2_sz_conf: when zero, BAR2 size conforms to
1394
+ *    PCIe specification
1395
+ * @efus_ign: efuse ignore
1396
+ * @nozip: ZIP disable
1397
+ * @pll_alt_matrix: select alternate PLL matrix
1398
+ * @pll_bwadj_denom: select CLKF denominator for
1399
+ *    BWADJ value
1400
+ * @chip_id: chip ID
1401
+ */
1402
+union fus_dat1 {
1403
+	u64 value;
1404
+	struct {
1405
+#if (defined(__BIG_ENDIAN_BITFIELD))
1406
+		u64 raz_57_63 : 7;
1407
+		u64 pll_mul : 3;
1408
+		u64 pll_half_dis : 1;
1409
+		u64 raz_43_52 : 10;
1410
+		u64 efus_lck : 3;
1411
+		u64 raz_26_39 : 14;
1412
+		u64 zip_info : 5;
1413
+		u64 bar2_sz_conf : 1;
1414
+		u64 efus_ign : 1;
1415
+		u64 nozip : 1;
1416
+		u64 raz_11_17 : 7;
1417
+		u64 pll_alt_matrix : 1;
1418
+		u64 pll_bwadj_denom : 2;
1419
+		u64 chip_id : 8;
1420
+#else
1421
+		u64 chip_id : 8;
1422
+		u64 pll_bwadj_denom : 2;
1423
+		u64 pll_alt_matrix : 1;
1424
+		u64 raz_11_17 : 7;
1425
+		u64 nozip : 1;
1426
+		u64 efus_ign : 1;
1427
+		u64 bar2_sz_conf : 1;
1428
+		u64 zip_info : 5;
1429
+		u64 raz_26_39 : 14;
1430
+		u64 efus_lck : 3;
1431
+		u64 raz_43_52 : 10;
1432
+		u64 pll_half_dis : 1;
1433
+		u64 pll_mul : 3;
1434
+		u64 raz_57_63 : 7;
1435
+#endif
1436
+	};
1437
+};
1438
+
10851439 #endif /* __NITROX_CSR_H */