.. | .. |
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14 | 14 | * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). |
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15 | 15 | */ |
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16 | 16 | |
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| 17 | +#include <asm/rmwcc.h> |
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| 18 | + |
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17 | 19 | #define ADDR (*(volatile long *)addr) |
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18 | 20 | |
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19 | 21 | /** |
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.. | .. |
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29 | 31 | */ |
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30 | 32 | static inline void sync_set_bit(long nr, volatile unsigned long *addr) |
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31 | 33 | { |
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32 | | - asm volatile("lock; bts %1,%0" |
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| 34 | + asm volatile("lock; " __ASM_SIZE(bts) " %1,%0" |
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33 | 35 | : "+m" (ADDR) |
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34 | 36 | : "Ir" (nr) |
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35 | 37 | : "memory"); |
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.. | .. |
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47 | 49 | */ |
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48 | 50 | static inline void sync_clear_bit(long nr, volatile unsigned long *addr) |
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49 | 51 | { |
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50 | | - asm volatile("lock; btr %1,%0" |
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| 52 | + asm volatile("lock; " __ASM_SIZE(btr) " %1,%0" |
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51 | 53 | : "+m" (ADDR) |
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52 | 54 | : "Ir" (nr) |
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53 | 55 | : "memory"); |
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.. | .. |
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64 | 66 | */ |
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65 | 67 | static inline void sync_change_bit(long nr, volatile unsigned long *addr) |
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66 | 68 | { |
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67 | | - asm volatile("lock; btc %1,%0" |
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| 69 | + asm volatile("lock; " __ASM_SIZE(btc) " %1,%0" |
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68 | 70 | : "+m" (ADDR) |
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69 | 71 | : "Ir" (nr) |
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70 | 72 | : "memory"); |
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.. | .. |
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78 | 80 | * This operation is atomic and cannot be reordered. |
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79 | 81 | * It also implies a memory barrier. |
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80 | 82 | */ |
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81 | | -static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr) |
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| 83 | +static inline bool sync_test_and_set_bit(long nr, volatile unsigned long *addr) |
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82 | 84 | { |
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83 | | - unsigned char oldbit; |
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84 | | - |
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85 | | - asm volatile("lock; bts %2,%1\n\tsetc %0" |
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86 | | - : "=qm" (oldbit), "+m" (ADDR) |
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87 | | - : "Ir" (nr) : "memory"); |
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88 | | - return oldbit; |
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| 85 | + return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(bts), *addr, c, "Ir", nr); |
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89 | 86 | } |
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90 | 87 | |
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91 | 88 | /** |
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.. | .. |
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98 | 95 | */ |
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99 | 96 | static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr) |
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100 | 97 | { |
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101 | | - unsigned char oldbit; |
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102 | | - |
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103 | | - asm volatile("lock; btr %2,%1\n\tsetc %0" |
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104 | | - : "=qm" (oldbit), "+m" (ADDR) |
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105 | | - : "Ir" (nr) : "memory"); |
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106 | | - return oldbit; |
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| 98 | + return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btr), *addr, c, "Ir", nr); |
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107 | 99 | } |
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108 | 100 | |
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109 | 101 | /** |
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.. | .. |
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116 | 108 | */ |
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117 | 109 | static inline int sync_test_and_change_bit(long nr, volatile unsigned long *addr) |
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118 | 110 | { |
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119 | | - unsigned char oldbit; |
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120 | | - |
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121 | | - asm volatile("lock; btc %2,%1\n\tsetc %0" |
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122 | | - : "=qm" (oldbit), "+m" (ADDR) |
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123 | | - : "Ir" (nr) : "memory"); |
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124 | | - return oldbit; |
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| 111 | + return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btc), *addr, c, "Ir", nr); |
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125 | 112 | } |
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126 | 113 | |
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127 | 114 | #define sync_test_bit(nr, addr) test_bit(nr, addr) |
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