hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811
kernel/arch/x86/include/asm/sync_bitops.h
....@@ -14,6 +14,8 @@
1414 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
1515 */
1616
17
+#include <asm/rmwcc.h>
18
+
1719 #define ADDR (*(volatile long *)addr)
1820
1921 /**
....@@ -29,7 +31,7 @@
2931 */
3032 static inline void sync_set_bit(long nr, volatile unsigned long *addr)
3133 {
32
- asm volatile("lock; bts %1,%0"
34
+ asm volatile("lock; " __ASM_SIZE(bts) " %1,%0"
3335 : "+m" (ADDR)
3436 : "Ir" (nr)
3537 : "memory");
....@@ -47,7 +49,7 @@
4749 */
4850 static inline void sync_clear_bit(long nr, volatile unsigned long *addr)
4951 {
50
- asm volatile("lock; btr %1,%0"
52
+ asm volatile("lock; " __ASM_SIZE(btr) " %1,%0"
5153 : "+m" (ADDR)
5254 : "Ir" (nr)
5355 : "memory");
....@@ -64,7 +66,7 @@
6466 */
6567 static inline void sync_change_bit(long nr, volatile unsigned long *addr)
6668 {
67
- asm volatile("lock; btc %1,%0"
69
+ asm volatile("lock; " __ASM_SIZE(btc) " %1,%0"
6870 : "+m" (ADDR)
6971 : "Ir" (nr)
7072 : "memory");
....@@ -78,14 +80,9 @@
7880 * This operation is atomic and cannot be reordered.
7981 * It also implies a memory barrier.
8082 */
81
-static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr)
83
+static inline bool sync_test_and_set_bit(long nr, volatile unsigned long *addr)
8284 {
83
- unsigned char oldbit;
84
-
85
- asm volatile("lock; bts %2,%1\n\tsetc %0"
86
- : "=qm" (oldbit), "+m" (ADDR)
87
- : "Ir" (nr) : "memory");
88
- return oldbit;
85
+ return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(bts), *addr, c, "Ir", nr);
8986 }
9087
9188 /**
....@@ -98,12 +95,7 @@
9895 */
9996 static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr)
10097 {
101
- unsigned char oldbit;
102
-
103
- asm volatile("lock; btr %2,%1\n\tsetc %0"
104
- : "=qm" (oldbit), "+m" (ADDR)
105
- : "Ir" (nr) : "memory");
106
- return oldbit;
98
+ return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btr), *addr, c, "Ir", nr);
10799 }
108100
109101 /**
....@@ -116,12 +108,7 @@
116108 */
117109 static inline int sync_test_and_change_bit(long nr, volatile unsigned long *addr)
118110 {
119
- unsigned char oldbit;
120
-
121
- asm volatile("lock; btc %2,%1\n\tsetc %0"
122
- : "=qm" (oldbit), "+m" (ADDR)
123
- : "Ir" (nr) : "memory");
124
- return oldbit;
111
+ return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btc), *addr, c, "Ir", nr);
125112 }
126113
127114 #define sync_test_bit(nr, addr) test_bit(nr, addr)