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hc
2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/arch/powerpc/kernel/tm.S
....@@ -92,13 +92,14 @@
9292 	blr
9393 EXPORT_SYMBOL_GPL(tm_abort);
9494 
95
-/* void tm_reclaim(struct thread_struct *thread,
95
+/*
96
+ * void tm_reclaim(struct thread_struct *thread,
9697  *		   uint8_t cause)
9798  *
9899  *	- Performs a full reclaim.  This destroys outstanding
99
- *	  transactions and updates thread->regs.tm_ckpt_* with the
100
- *	  original checkpointed state.  Note that thread->regs is
101
- *	  unchanged.
100
+ *	  transactions and updates thread.ckpt_regs, thread.ckfp_state and
101
+ *	  thread.ckvr_state with the original checkpointed state.  Note that
102
+ *	  thread->regs is unchanged.
102103  *
103104  * Purpose is to both abort transactions of, and preserve the state of,
104105  * a transactions at a context switch. We preserve/restore both sets of process
....@@ -120,6 +121,13 @@
120121 
121122 	std	r3, STK_PARAM(R3)(r1)
122123 	SAVE_NVGPRS(r1)
124
+
125
+	/*
126
+	 * Save kernel live AMR since it will be clobbered by treclaim
127
+	 * but can be used elsewhere later in kernel space.
128
+	 */
129
+	mfspr	r3, SPRN_AMR
130
+	std	r3, TM_FRAME_L1(r1)
123131 
124132 	/* We need to setup MSR for VSX register save instructions. */
125133 	mfmsr	r14
....@@ -147,7 +155,7 @@
147155 	/* Stash the stack pointer away for use after reclaim */
148156 	std	r1, PACAR1(r13)
149157 
150
-	/* Clear MSR RI since we are about to change r1, EE is already off. */
158
+	/* Clear MSR RI since we are about to use SCRATCH0, EE is already off */
151159 	li	r5, 0
152160 	mtmsrd	r5, 1
153161 
....@@ -163,15 +171,16 @@
163171 	 */
164172 	TRECLAIM(R4)				/* Cause in r4 */
165173 
166
-	/* ******************** GPRs ******************** */
167
-	/* Stash the checkpointed r13 away in the scratch SPR and get the real
168
-	 *  paca
174
+	/*
175
+	 * ******************** GPRs ********************
176
+	 * Stash the checkpointed r13 in the scratch SPR and get the real paca.
169177 	 */
170178 	SET_SCRATCH0(r13)
171179 	GET_PACA(r13)
172180 
173
-	/* Stash the checkpointed r1 away in paca tm_scratch and get the real
174
-	 * stack pointer back
181
+	/*
182
+	 * Stash the checkpointed r1 away in paca->tm_scratch and get the real
183
+	 * stack pointer back into r1.
175184 	 */
176185 	std	r1, PACATMSCRATCH(r13)
177186 	ld	r1, PACAR1(r13)
....@@ -209,14 +218,15 @@
209218 
210219 	addi	r7, r12, PT_CKPT_REGS		/* Thread's ckpt_regs */
211220 
212
-	/* Make r7 look like an exception frame so that we
213
-	 * can use the neat GPRx(n) macros.  r7 is NOT a pt_regs ptr!
221
+	/*
222
+	 * Make r7 look like an exception frame so that we can use the neat
223
+	 * GPRx(n) macros. r7 is NOT a pt_regs ptr!
214224 	 */
215225 	subi	r7, r7, STACK_FRAME_OVERHEAD
216226 
217227 	/* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
218228 	SAVE_GPR(0, r7)				/* user r0 */
219
-	SAVE_GPR(2, r7)			/* user r2 */
229
+	SAVE_GPR(2, r7)				/* user r2 */
220230 	SAVE_4GPRS(3, r7)			/* user r3-r6 */
221231 	SAVE_GPR(8, r7)				/* user r8 */
222232 	SAVE_GPR(9, r7)				/* user r9 */
....@@ -237,11 +247,12 @@
237247 	/* ******************** NIP ******************** */
238248 	mfspr	r3, SPRN_TFHAR
239249 	std	r3, _NIP(r7)			/* Returns to failhandler */
240
-	/* The checkpointed NIP is ignored when rescheduling/rechkpting,
250
+	/*
251
+	 * The checkpointed NIP is ignored when rescheduling/rechkpting,
241252 	 * but is used in signal return to 'wind back' to the abort handler.
242253 	 */
243254 
244
-	/* ******************** CR,LR,CCR,MSR ********** */
255
+	/* ***************** CTR, LR, CR, XER ********** */
245256 	mfctr	r3
246257 	mflr	r4
247258 	mfcr	r5
....@@ -252,7 +263,6 @@
252263 	std	r5, _CCR(r7)
253264 	std	r6, _XER(r7)
254265 
255
-
256266 	/* ******************** TAR, DSCR ********** */
257267 	mfspr	r3, SPRN_TAR
258268 	mfspr	r4, SPRN_DSCR
....@@ -260,12 +270,17 @@
260270 	std	r3, THREAD_TM_TAR(r12)
261271 	std	r4, THREAD_TM_DSCR(r12)
262272 
263
-	/* MSR and flags:  We don't change CRs, and we don't need to alter
264
-	 * MSR.
273
+        /* ******************** AMR **************** */
274
+        mfspr	r3, SPRN_AMR
275
+        std	r3, THREAD_TM_AMR(r12)
276
+
277
+	/*
278
+	 * MSR and flags: We don't change CRs, and we don't need to alter MSR.
265279 	 */
266280 
267281 
268
-	/* ******************** FPR/VR/VSRs ************
282
+	/*
283
+	 * ******************** FPR/VR/VSRs ************
269284 	 * After reclaiming, capture the checkpointed FPRs/VRs.
270285 	 *
271286 	 * We enabled VEC/FP/VSX in the msr above, so we can execute these
....@@ -275,7 +290,7 @@
275290 
276291 	/* Altivec (VEC/VMX/VR)*/
277292 	addi	r7, r3, THREAD_CKVRSTATE
278
-	SAVE_32VRS(0, r6, r7)	/* r6 scratch, r7 transact vr state */
293
+	SAVE_32VRS(0, r6, r7)	/* r6 scratch, r7 ckvr_state */
279294 	mfvscr	v0
280295 	li	r6, VRSTATE_VSCR
281296 	stvx	v0, r7, r6
....@@ -286,12 +301,13 @@
286301 
287302 	/* Floating Point (FP) */
288303 	addi	r7, r3, THREAD_CKFPSTATE
289
-	SAVE_32FPRS_VSRS(0, R6, R7)	/* r6 scratch, r7 transact fp state */
304
+	SAVE_32FPRS_VSRS(0, R6, R7)	/* r6 scratch, r7 ckfp_state */
290305 	mffs    fr0
291306 	stfd    fr0,FPSTATE_FPSCR(r7)
292307 
293308 
294
-	/* TM regs, incl TEXASR -- these live in thread_struct.  Note they've
309
+	/*
310
+	 * TM regs, incl TEXASR -- these live in thread_struct.  Note they've
295311 	 * been updated by the treclaim, to explain to userland the failure
296312 	 * cause (aborted).
297313 	 */
....@@ -302,7 +318,9 @@
302318 	std	r3, THREAD_TM_TFHAR(r12)
303319 	std	r4, THREAD_TM_TFIAR(r12)
304320 
305
-	/* AMR is checkpointed too, but is unsupported by Linux. */
321
+	/* Restore kernel live AMR */
322
+	ld	r8, TM_FRAME_L1(r1)
323
+	mtspr	SPRN_AMR, r8
306324 
307325 	/* Restore original MSR/IRQ state & clear TM mode */
308326 	ld	r14, TM_FRAME_L0(r1)		/* Orig MSR */
....@@ -327,7 +345,7 @@
327345 	blr
328346 
329347 
330
-       /*
348
+	/*
331349 	 * void __tm_recheckpoint(struct thread_struct *thread)
332350 	 *	- Restore the checkpointed register state saved by tm_reclaim
333351 	 *	  when we switch_to a process.
....@@ -343,17 +361,26 @@
343361 	std	r2, STK_GOT(r1)
344362 	stdu	r1, -TM_FRAME_SIZE(r1)
345363 
346
-	/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
364
+	/*
365
+	 * We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
347366 	 * This is used for backing up the NVGPRs:
348367 	 */
349368 	SAVE_NVGPRS(r1)
369
+
370
+	/*
371
+	 * Save kernel live AMR since it will be clobbered for trechkpt
372
+	 * but can be used elsewhere later in kernel space.
373
+	 */
374
+	mfspr	r8, SPRN_AMR
375
+	std	r8, TM_FRAME_L0(r1)
350376 
351377 	/* Load complete register state from ts_ckpt* registers */
352378 
353379 	addi	r7, r3, PT_CKPT_REGS		/* Thread's ckpt_regs */
354380 
355
-	/* Make r7 look like an exception frame so that we
356
-	 * can use the neat GPRx(n) macros.  r7 is now NOT a pt_regs ptr!
381
+	/*
382
+	 * Make r7 look like an exception frame so that we can use the neat
383
+	 * GPRx(n) macros. r7 is now NOT a pt_regs ptr!
357384 	 */
358385 	subi	r7, r7, STACK_FRAME_OVERHEAD
359386 
....@@ -396,7 +423,7 @@
396423 
397424 restore_gprs:
398425 
399
-	/* ******************** CR,LR,CCR,MSR ********** */
426
+	/* ****************** CTR, LR, XER ************* */
400427 	ld	r4, _CTR(r7)
401428 	ld	r5, _LINK(r7)
402429 	ld	r8, _XER(r7)
....@@ -408,6 +435,10 @@
408435 	/* ******************** TAR ******************** */
409436 	ld	r4, THREAD_TM_TAR(r3)
410437 	mtspr	SPRN_TAR,	r4
438
+
439
+	/* ******************** AMR ******************** */
440
+	ld	r4, THREAD_TM_AMR(r3)
441
+	mtspr	SPRN_AMR, r4
411442 
412443 	/* Load up the PPR and DSCR in GPRs only at this stage */
413444 	ld	r5, THREAD_TM_DSCR(r3)
....@@ -421,14 +452,15 @@
421452 
422453 	REST_NVGPRS(r7)				/* GPR14-31 */
423454 
424
-	/* Load up PPR and DSCR here so we don't run with user values for long
425
-	 */
455
+	/* Load up PPR and DSCR here so we don't run with user values for long */
426456 	mtspr	SPRN_DSCR, r5
427457 	mtspr	SPRN_PPR, r6
428458 
429
-	/* Do final sanity check on TEXASR to make sure FS is set.  Do this
459
+	/*
460
+	 * Do final sanity check on TEXASR to make sure FS is set. Do this
430461 	 * here before we load up the userspace r1 so any bugs we hit will get
431
-	 * a call chain */
462
+	 * a call chain.
463
+	 */
432464 	mfspr	r5, SPRN_TEXASR
433465 	srdi	r5, r5, 16
434466 	li	r6, (TEXASR_FS)@h
....@@ -436,8 +468,9 @@
436468 1:	tdeqi	r6, 0
437469 	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
438470 
439
-	/* Do final sanity check on MSR to make sure we are not transactional
440
-	 * or suspended
471
+	/*
472
+	 * Do final sanity check on MSR to make sure we are not transactional
473
+	 * or suspended.
441474 	 */
442475 	mfmsr   r6
443476 	li	r5, (MSR_TS_MASK)@higher
....@@ -453,8 +486,8 @@
453486 	REST_GPR(6, r7)
454487 
455488 	/*
456
-	 * Store r1 and r5 on the stack so that we can access them
457
-	 * after we clear MSR RI.
489
+	 * Store r1 and r5 on the stack so that we can access them after we
490
+	 * clear MSR RI.
458491 	 */
459492 
460493 	REST_GPR(5, r7)
....@@ -464,7 +497,7 @@
464497 
465498 	REST_GPR(7, r7)
466499 
467
-	/* Clear MSR RI since we are about to change r1. EE is already off */
500
+	/* Clear MSR RI since we are about to use SCRATCH0. EE is already off */
468501 	li	r5, 0
469502 	mtmsrd	r5, 1
470503 
....@@ -484,7 +517,8 @@
484517 
485518 	HMT_MEDIUM
486519 
487
-	/* Our transactional state has now changed.
520
+	/*
521
+	 * Our transactional state has now changed.
488522 	 *
489523 	 * Now just get out of here.  Transactional (current) state will be
490524 	 * updated once restore is called on the return path in the _switch-ed
....@@ -498,6 +532,10 @@
498532 	li	r4, MSR_RI
499533 	mtmsrd	r4, 1
500534 
535
+	/* Restore kernel live AMR */
536
+	ld	r8, TM_FRAME_L0(r1)
537
+	mtspr	SPRN_AMR, r8
538
+
501539 	REST_NVGPRS(r1)
502540 
503541 	addi    r1, r1, TM_FRAME_SIZE