disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/arch/mips/lantiq/xway/dma.c
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@@ -1,16 +1,5 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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- *   This program is free software; you can redistribute it and/or modify it
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- *   under the terms of the GNU General Public License version 2 as published
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- *   by the Free Software Foundation.
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- *
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- *   This program is distributed in the hope that it will be useful,
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- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
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- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- *   GNU General Public License for more details.
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- *
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- *   You should have received a copy of the GNU General Public License
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- *   along with this program; if not, write to the Free Software
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- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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  *
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  *   Copyright (C) 2011 John Crispin <john@phrozen.org>
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  */
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@@ -51,7 +40,11 @@
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 #define DMA_IRQ_ACK		0x7e		/* IRQ status register */
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 #define DMA_POLL		BIT(31)		/* turn on channel polling */
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 #define DMA_CLK_DIV4		BIT(6)		/* polling clock divider */
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-#define DMA_2W_BURST		BIT(1)		/* 2 word burst length */
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+#define DMA_PCTRL_2W_BURST	0x1		/* 2 word burst length */
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+#define DMA_PCTRL_4W_BURST	0x2		/* 4 word burst length */
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+#define DMA_PCTRL_8W_BURST	0x3		/* 8 word burst length */
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+#define DMA_TX_BURST_SHIFT	4		/* tx burst shift */
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+#define DMA_RX_BURST_SHIFT	2		/* rx burst shift */
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 #define DMA_ETOP_ENDIANNESS	(0xf << 8) /* endianness swap etop channels */
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 #define DMA_WEIGHT	(BIT(17) | BIT(16))	/* default channel wheight */
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@@ -107,7 +100,6 @@
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 	spin_lock_irqsave(&ltq_dma_lock, flag);
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 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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 	ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
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-	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
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 	spin_unlock_irqrestore(&ltq_dma_lock, flag);
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 }
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 EXPORT_SYMBOL_GPL(ltq_dma_open);
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@@ -131,9 +123,9 @@
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 	unsigned long flags;
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 	ch->desc = 0;
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-	ch->desc_base = dma_zalloc_coherent(ch->dev,
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-				LTQ_DESC_NUM * LTQ_DESC_SIZE,
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-				&ch->phys, GFP_ATOMIC);
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+	ch->desc_base = dma_alloc_coherent(ch->dev,
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+					   LTQ_DESC_NUM * LTQ_DESC_SIZE,
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+					   &ch->phys, GFP_ATOMIC);
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 	spin_lock_irqsave(&ltq_dma_lock, flags);
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 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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@@ -203,7 +195,8 @@
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 		break;
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 	case DMA_PORT_DEU:
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-		ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
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+		ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
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+			(DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
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 			LTQ_DMA_PCTRL);
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 		break;
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