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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | 3 | * arch/arm64/include/asm/cpucaps.h |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2016 ARM Ltd. |
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5 | | - * |
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6 | | - * This program is free software: you can redistribute it and/or modify |
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7 | | - * it under the terms of the GNU General Public License version 2 as |
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8 | | - * published by the Free Software Foundation. |
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9 | | - * |
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10 | | - * This program is distributed in the hope that it will be useful, |
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11 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | | - * GNU General Public License for more details. |
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14 | | - * |
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15 | | - * You should have received a copy of the GNU General Public License |
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16 | | - * along with this program. If not, see <http://www.gnu.org/licenses/>. |
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17 | 6 | */ |
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18 | 7 | #ifndef __ASM_CPUCAPS_H |
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19 | 8 | #define __ASM_CPUCAPS_H |
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.. | .. |
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31 | 20 | #define ARM64_ALT_PAN_NOT_UAO 10 |
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32 | 21 | #define ARM64_HAS_VIRT_HOST_EXTN 11 |
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33 | 22 | #define ARM64_WORKAROUND_CAVIUM_27456 12 |
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34 | | -#define ARM64_HAS_32BIT_EL0 13 |
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35 | | -#define ARM64_HARDEN_EL2_VECTORS 14 |
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36 | | -#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15 |
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| 23 | +/* Unreliable: use system_supports_32bit_el0() instead. */ |
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| 24 | +#define ARM64_HAS_32BIT_EL0_DO_NOT_USE 13 |
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| 25 | +#define ARM64_SPECTRE_V3A 14 |
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| 26 | +#define ARM64_HAS_CNP 15 |
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37 | 27 | #define ARM64_HAS_NO_FPSIMD 16 |
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38 | 28 | #define ARM64_WORKAROUND_REPEAT_TLBI 17 |
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39 | 29 | #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 |
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.. | .. |
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42 | 32 | #define ARM64_HAS_DCPOP 21 |
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43 | 33 | #define ARM64_SVE 22 |
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44 | 34 | #define ARM64_UNMAP_KERNEL_AT_EL0 23 |
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45 | | -#define ARM64_HARDEN_BRANCH_PREDICTOR 24 |
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| 35 | +#define ARM64_SPECTRE_V2 24 |
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46 | 36 | #define ARM64_HAS_RAS_EXTN 25 |
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47 | 37 | #define ARM64_WORKAROUND_843419 26 |
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48 | 38 | #define ARM64_HAS_CACHE_IDC 27 |
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49 | 39 | #define ARM64_HAS_CACHE_DIC 28 |
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50 | 40 | #define ARM64_HW_DBM 29 |
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51 | | -#define ARM64_SSBD 30 |
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| 41 | +#define ARM64_SPECTRE_V4 30 |
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52 | 42 | #define ARM64_MISMATCHED_CACHE_TYPE 31 |
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53 | 43 | #define ARM64_HAS_STAGE2_FWB 32 |
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54 | | -#define ARM64_WORKAROUND_1463225 33 |
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| 44 | +#define ARM64_HAS_CRC32 33 |
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55 | 45 | #define ARM64_SSBS 34 |
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56 | | -#define ARM64_WORKAROUND_1542419 35 |
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| 46 | +#define ARM64_WORKAROUND_1418040 35 |
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| 47 | +#define ARM64_HAS_SB 36 |
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| 48 | +#define ARM64_WORKAROUND_SPECULATIVE_AT 37 |
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| 49 | +#define ARM64_HAS_ADDRESS_AUTH_ARCH 38 |
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| 50 | +#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39 |
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| 51 | +#define ARM64_HAS_GENERIC_AUTH_ARCH 40 |
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| 52 | +#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41 |
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| 53 | +#define ARM64_HAS_IRQ_PRIO_MASKING 42 |
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| 54 | +#define ARM64_HAS_DCPODP 43 |
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| 55 | +#define ARM64_WORKAROUND_1463225 44 |
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| 56 | +#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45 |
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| 57 | +#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46 |
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| 58 | +#define ARM64_WORKAROUND_1542419 47 |
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| 59 | +#define ARM64_HAS_E0PD 48 |
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| 60 | +#define ARM64_HAS_RNG 49 |
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| 61 | +#define ARM64_HAS_AMU_EXTN 50 |
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| 62 | +#define ARM64_HAS_ADDRESS_AUTH 51 |
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| 63 | +#define ARM64_HAS_GENERIC_AUTH 52 |
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| 64 | +#define ARM64_HAS_32BIT_EL1 53 |
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| 65 | +#define ARM64_BTI 54 |
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| 66 | +#define ARM64_HAS_ARMv8_4_TTL 55 |
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| 67 | +#define ARM64_HAS_TLB_RANGE 56 |
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| 68 | +#define ARM64_MTE 57 |
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| 69 | +#define ARM64_WORKAROUND_1508412 58 |
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| 70 | +#define ARM64_HAS_LDAPR 59 |
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| 71 | +#define ARM64_KVM_PROTECTED_MODE 60 |
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| 72 | +#define ARM64_WORKAROUND_TSB_FLUSH_FAILURE 61 |
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| 73 | +#define ARM64_SPECTRE_BHB 62 |
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| 74 | +#define ARM64_WORKAROUND_2457168 63 |
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| 75 | +#define ARM64_WORKAROUND_1742098 64 |
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57 | 76 | |
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58 | | -/* kabi: reserve 36 - 62 for future cpu capabilities */ |
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59 | | -#define ARM64_NCAPS 62 |
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| 77 | +/* kabi: reserve 65 - 76 for future cpu capabilities */ |
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| 78 | +#define ARM64_NCAPS 76 |
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60 | 79 | |
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61 | 80 | #endif /* __ASM_CPUCAPS_H */ |
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