.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * linux/arch/arm/mach-rpc/dma.c |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 1998 Russell King |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify |
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7 | | - * it under the terms of the GNU General Public License version 2 as |
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8 | | - * published by the Free Software Foundation. |
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9 | 6 | * |
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10 | 7 | * DMA functions specific to RiscPC architecture |
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11 | 8 | */ |
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.. | .. |
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27 | 24 | |
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28 | 25 | struct iomd_dma { |
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29 | 26 | struct dma_struct dma; |
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30 | | - unsigned int state; |
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31 | | - unsigned long base; /* Controller base address */ |
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| 27 | + void __iomem *base; /* Controller base address */ |
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32 | 28 | int irq; /* Controller IRQ */ |
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33 | | - struct scatterlist cur_sg; /* Current controller buffer */ |
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| 29 | + unsigned int state; |
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| 30 | + dma_addr_t cur_addr; |
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| 31 | + unsigned int cur_len; |
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34 | 32 | dma_addr_t dma_addr; |
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35 | 33 | unsigned int dma_len; |
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36 | 34 | }; |
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.. | .. |
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53 | 51 | #define CR (IOMD_IO0CR - IOMD_IO0CURA) |
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54 | 52 | #define ST (IOMD_IO0ST - IOMD_IO0CURA) |
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55 | 53 | |
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56 | | -static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma) |
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| 54 | +static void iomd_get_next_sg(struct iomd_dma *idma) |
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57 | 55 | { |
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58 | 56 | unsigned long end, offset, flags = 0; |
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59 | 57 | |
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60 | 58 | if (idma->dma.sg) { |
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61 | | - sg->dma_address = idma->dma_addr; |
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62 | | - offset = sg->dma_address & ~PAGE_MASK; |
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| 59 | + idma->cur_addr = idma->dma_addr; |
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| 60 | + offset = idma->cur_addr & ~PAGE_MASK; |
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63 | 61 | |
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64 | 62 | end = offset + idma->dma_len; |
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65 | 63 | |
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.. | .. |
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69 | 67 | if (offset + TRANSFER_SIZE >= end) |
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70 | 68 | flags |= DMA_END_L; |
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71 | 69 | |
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72 | | - sg->length = end - TRANSFER_SIZE; |
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| 70 | + idma->cur_len = end - TRANSFER_SIZE; |
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73 | 71 | |
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74 | 72 | idma->dma_len -= end - offset; |
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75 | 73 | idma->dma_addr += end - offset; |
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.. | .. |
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87 | 85 | } |
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88 | 86 | } else { |
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89 | 87 | flags = DMA_END_S | DMA_END_L; |
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90 | | - sg->dma_address = 0; |
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91 | | - sg->length = 0; |
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| 88 | + idma->cur_addr = 0; |
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| 89 | + idma->cur_len = 0; |
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92 | 90 | } |
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93 | 91 | |
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94 | | - sg->length |= flags; |
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| 92 | + idma->cur_len |= flags; |
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95 | 93 | } |
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96 | 94 | |
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97 | 95 | static irqreturn_t iomd_dma_handle(int irq, void *dev_id) |
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98 | 96 | { |
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99 | 97 | struct iomd_dma *idma = dev_id; |
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100 | | - unsigned long base = idma->base; |
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| 98 | + void __iomem *base = idma->base; |
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| 99 | + unsigned int state = idma->state; |
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| 100 | + unsigned int status, cur, end; |
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101 | 101 | |
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102 | 102 | do { |
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103 | | - unsigned int status; |
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104 | | - |
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105 | | - status = iomd_readb(base + ST); |
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| 103 | + status = readb(base + ST); |
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106 | 104 | if (!(status & DMA_ST_INT)) |
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107 | | - return IRQ_HANDLED; |
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| 105 | + goto out; |
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108 | 106 | |
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109 | | - if ((idma->state ^ status) & DMA_ST_AB) |
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110 | | - iomd_get_next_sg(&idma->cur_sg, idma); |
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| 107 | + if ((state ^ status) & DMA_ST_AB) |
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| 108 | + iomd_get_next_sg(idma); |
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111 | 109 | |
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112 | | - switch (status & (DMA_ST_OFL | DMA_ST_AB)) { |
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113 | | - case DMA_ST_OFL: /* OIA */ |
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114 | | - case DMA_ST_AB: /* .IB */ |
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115 | | - iomd_writel(idma->cur_sg.dma_address, base + CURA); |
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116 | | - iomd_writel(idma->cur_sg.length, base + ENDA); |
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117 | | - idma->state = DMA_ST_AB; |
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118 | | - break; |
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119 | | - |
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120 | | - case DMA_ST_OFL | DMA_ST_AB: /* OIB */ |
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121 | | - case 0: /* .IA */ |
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122 | | - iomd_writel(idma->cur_sg.dma_address, base + CURB); |
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123 | | - iomd_writel(idma->cur_sg.length, base + ENDB); |
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124 | | - idma->state = 0; |
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125 | | - break; |
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| 110 | + // This efficiently implements state = OFL != AB ? AB : 0 |
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| 111 | + state = ((status >> 2) ^ status) & DMA_ST_AB; |
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| 112 | + if (state) { |
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| 113 | + cur = CURA; |
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| 114 | + end = ENDA; |
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| 115 | + } else { |
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| 116 | + cur = CURB; |
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| 117 | + end = ENDB; |
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126 | 118 | } |
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| 119 | + writel(idma->cur_addr, base + cur); |
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| 120 | + writel(idma->cur_len, base + end); |
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127 | 121 | |
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128 | 122 | if (status & DMA_ST_OFL && |
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129 | | - idma->cur_sg.length == (DMA_END_S|DMA_END_L)) |
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| 123 | + idma->cur_len == (DMA_END_S|DMA_END_L)) |
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130 | 124 | break; |
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131 | 125 | } while (1); |
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132 | 126 | |
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133 | | - idma->state = ~DMA_ST_AB; |
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| 127 | + state = ~DMA_ST_AB; |
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134 | 128 | disable_irq_nosync(irq); |
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135 | | - |
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| 129 | +out: |
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| 130 | + idma->state = state; |
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136 | 131 | return IRQ_HANDLED; |
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137 | 132 | } |
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138 | 133 | |
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.. | .. |
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151 | 146 | free_irq(idma->irq, idma); |
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152 | 147 | } |
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153 | 148 | |
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| 149 | +static struct device isa_dma_dev = { |
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| 150 | + .init_name = "fallback device", |
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| 151 | + .coherent_dma_mask = ~(dma_addr_t)0, |
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| 152 | + .dma_mask = &isa_dma_dev.coherent_dma_mask, |
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| 153 | +}; |
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| 154 | + |
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154 | 155 | static void iomd_enable_dma(unsigned int chan, dma_t *dma) |
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155 | 156 | { |
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156 | 157 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
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157 | | - unsigned long dma_base = idma->base; |
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| 158 | + void __iomem *base = idma->base; |
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158 | 159 | unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; |
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159 | 160 | |
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160 | 161 | if (idma->dma.invalid) { |
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.. | .. |
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168 | 169 | idma->dma.sg = &idma->dma.buf; |
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169 | 170 | idma->dma.sgcount = 1; |
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170 | 171 | idma->dma.buf.length = idma->dma.count; |
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171 | | - idma->dma.buf.dma_address = dma_map_single(NULL, |
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| 172 | + idma->dma.buf.dma_address = dma_map_single(&isa_dma_dev, |
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172 | 173 | idma->dma.addr, idma->dma.count, |
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173 | 174 | idma->dma.dma_mode == DMA_MODE_READ ? |
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174 | 175 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
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.. | .. |
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177 | 178 | idma->dma_addr = idma->dma.sg->dma_address; |
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178 | 179 | idma->dma_len = idma->dma.sg->length; |
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179 | 180 | |
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180 | | - iomd_writeb(DMA_CR_C, dma_base + CR); |
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| 181 | + writeb(DMA_CR_C, base + CR); |
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181 | 182 | idma->state = DMA_ST_AB; |
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182 | 183 | } |
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183 | 184 | |
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184 | 185 | if (idma->dma.dma_mode == DMA_MODE_READ) |
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185 | 186 | ctrl |= DMA_CR_D; |
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186 | 187 | |
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187 | | - iomd_writeb(ctrl, dma_base + CR); |
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| 188 | + writeb(ctrl, base + CR); |
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188 | 189 | enable_irq(idma->irq); |
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189 | 190 | } |
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190 | 191 | |
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191 | 192 | static void iomd_disable_dma(unsigned int chan, dma_t *dma) |
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192 | 193 | { |
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193 | 194 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
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194 | | - unsigned long dma_base = idma->base; |
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| 195 | + void __iomem *base = idma->base; |
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195 | 196 | unsigned long flags; |
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196 | 197 | |
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197 | 198 | local_irq_save(flags); |
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198 | 199 | if (idma->state != ~DMA_ST_AB) |
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199 | 200 | disable_irq(idma->irq); |
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200 | | - iomd_writeb(0, dma_base + CR); |
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| 201 | + writeb(0, base + CR); |
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201 | 202 | local_irq_restore(flags); |
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202 | 203 | } |
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203 | 204 | |
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.. | .. |
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360 | 361 | */ |
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361 | 362 | iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT); |
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362 | 363 | |
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363 | | - iomd_dma[DMA_0].base = IOMD_IO0CURA; |
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| 364 | + iomd_dma[DMA_0].base = IOMD_BASE + IOMD_IO0CURA; |
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364 | 365 | iomd_dma[DMA_0].irq = IRQ_DMA0; |
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365 | | - iomd_dma[DMA_1].base = IOMD_IO1CURA; |
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| 366 | + iomd_dma[DMA_1].base = IOMD_BASE + IOMD_IO1CURA; |
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366 | 367 | iomd_dma[DMA_1].irq = IRQ_DMA1; |
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367 | | - iomd_dma[DMA_2].base = IOMD_IO2CURA; |
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| 368 | + iomd_dma[DMA_2].base = IOMD_BASE + IOMD_IO2CURA; |
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368 | 369 | iomd_dma[DMA_2].irq = IRQ_DMA2; |
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369 | | - iomd_dma[DMA_3].base = IOMD_IO3CURA; |
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| 370 | + iomd_dma[DMA_3].base = IOMD_BASE + IOMD_IO3CURA; |
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370 | 371 | iomd_dma[DMA_3].irq = IRQ_DMA3; |
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371 | | - iomd_dma[DMA_S0].base = IOMD_SD0CURA; |
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| 372 | + iomd_dma[DMA_S0].base = IOMD_BASE + IOMD_SD0CURA; |
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372 | 373 | iomd_dma[DMA_S0].irq = IRQ_DMAS0; |
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373 | | - iomd_dma[DMA_S1].base = IOMD_SD1CURA; |
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| 374 | + iomd_dma[DMA_S1].base = IOMD_BASE + IOMD_SD1CURA; |
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374 | 375 | iomd_dma[DMA_S1].irq = IRQ_DMAS1; |
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375 | 376 | |
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376 | 377 | for (i = DMA_0; i <= DMA_S1; i++) { |
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