.. | .. |
---|
2 | 2 | |
---|
3 | 3 | Required properties: |
---|
4 | 4 | - compatible: 'amlogic,axg-tdmin' or |
---|
5 | | - 'amlogic,axg-tdmout' |
---|
| 5 | + 'amlogic,axg-tdmout' or |
---|
| 6 | + 'amlogic,g12a-tdmin' or |
---|
| 7 | + 'amlogic,g12a-tdmout' or |
---|
| 8 | + 'amlogic,sm1-tdmin' or |
---|
| 9 | + 'amlogic,sm1-tdmout |
---|
6 | 10 | - reg: physical base address of the controller and length of memory |
---|
7 | 11 | mapped region. |
---|
8 | 12 | - clocks: list of clock phandle, one for each entry clock-names. |
---|
.. | .. |
---|
13 | 17 | * "lrclk" : sample clock |
---|
14 | 18 | * "lrclk_sel": sample clock input multiplexer |
---|
15 | 19 | |
---|
16 | | -Example of TDMOUT_A on the A113 SoC: |
---|
| 20 | +Optional property: |
---|
| 21 | +- resets: phandle to the dedicated reset line of the tdm formatter. |
---|
| 22 | + |
---|
| 23 | +Example of TDMOUT_A on the S905X2 SoC: |
---|
17 | 24 | |
---|
18 | 25 | tdmout_a: audio-controller@500 { |
---|
19 | 26 | compatible = "amlogic,axg-tdmout"; |
---|
20 | 27 | reg = <0x0 0x500 0x0 0x40>; |
---|
| 28 | + resets = <&clkc_audio AUD_RESET_TDMOUT_A>; |
---|
21 | 29 | clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, |
---|
22 | 30 | <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, |
---|
23 | 31 | <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, |
---|