.. | .. |
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9 | 9 | such as network interfaces, crypto accelerator instances, L2 switches, |
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10 | 10 | etc. |
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11 | 11 | |
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| 12 | +For an overview of the DPAA2 architecture and fsl-mc bus see: |
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| 13 | +Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst |
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| 14 | + |
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| 15 | +As described in the above overview, all DPAA2 objects in a DPRC share the |
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| 16 | +same hardware "isolation context" and a 10-bit value called an ICID |
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| 17 | +(isolation context id) is expressed by the hardware to identify |
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| 18 | +the requester. |
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| 19 | + |
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| 20 | +The generic 'iommus' property is insufficient to describe the relationship |
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| 21 | +between ICIDs and IOMMUs, so an iommu-map property is used to define |
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| 22 | +the set of possible ICIDs under a root DPRC and how they map to |
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| 23 | +an IOMMU. |
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| 24 | + |
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| 25 | +For generic IOMMU bindings, see |
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| 26 | +Documentation/devicetree/bindings/iommu/iommu.txt. |
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| 27 | + |
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| 28 | +For arm-smmu binding, see: |
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| 29 | +Documentation/devicetree/bindings/iommu/arm,smmu.yaml. |
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| 30 | + |
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| 31 | +The MSI writes are accompanied by sideband data which is derived from the ICID. |
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| 32 | +The msi-map property is used to associate the devices with both the ITS |
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| 33 | +controller and the sideband data which accompanies the writes. |
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| 34 | + |
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| 35 | +For generic MSI bindings, see |
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| 36 | +Documentation/devicetree/bindings/interrupt-controller/msi.txt. |
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| 37 | + |
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| 38 | +For GICv3 and GIC ITS bindings, see: |
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| 39 | +Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml. |
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| 40 | + |
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12 | 41 | Required properties: |
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13 | 42 | |
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14 | 43 | - compatible |
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.. | .. |
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29 | 58 | -the second region is the MC control registers. This |
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30 | 59 | region may not be present in some scenarios, such |
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31 | 60 | as in the device tree presented to a virtual machine. |
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32 | | - |
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33 | | - - msi-parent |
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34 | | - Value type: <phandle> |
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35 | | - Definition: Must be present and point to the MSI controller node |
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36 | | - handling message interrupts for the MC. |
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37 | 61 | |
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38 | 62 | - ranges |
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39 | 63 | Value type: <prop-encoded-array> |
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.. | .. |
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88 | 112 | Value type: <phandle> |
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89 | 113 | Definition: Specifies the phandle to the PHY device node associated |
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90 | 114 | with the this dpmac. |
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| 115 | +Optional properties: |
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| 116 | + |
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| 117 | +- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier |
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| 118 | + data. |
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| 119 | + |
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| 120 | + The property is an arbitrary number of tuples of |
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| 121 | + (icid-base,iommu,iommu-base,length). |
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| 122 | + |
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| 123 | + Any ICID i in the interval [icid-base, icid-base + length) is |
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| 124 | + associated with the listed IOMMU, with the iommu-specifier |
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| 125 | + (i - icid-base + iommu-base). |
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| 126 | + |
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| 127 | +- msi-map: Maps an ICID to a GIC ITS and associated msi-specifier |
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| 128 | + data. |
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| 129 | + |
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| 130 | + The property is an arbitrary number of tuples of |
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| 131 | + (icid-base,gic-its,msi-base,length). |
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| 132 | + |
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| 133 | + Any ICID in the interval [icid-base, icid-base + length) is |
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| 134 | + associated with the listed GIC ITS, with the msi-specifier |
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| 135 | + (i - icid-base + msi-base). |
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| 136 | + |
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| 137 | +Deprecated properties: |
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| 138 | + |
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| 139 | + - msi-parent |
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| 140 | + Value type: <phandle> |
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| 141 | + Definition: Describes the MSI controller node handling message |
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| 142 | + interrupts for the MC. When there is no translation |
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| 143 | + between the ICID and deviceID this property can be used |
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| 144 | + to describe the MSI controller used by the devices on the |
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| 145 | + mc-bus. |
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| 146 | + The use of this property for mc-bus is deprecated. Please |
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| 147 | + use msi-map. |
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91 | 148 | |
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92 | 149 | Example: |
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| 150 | + |
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| 151 | + smmu: iommu@5000000 { |
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| 152 | + compatible = "arm,mmu-500"; |
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| 153 | + #iommu-cells = <1>; |
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| 154 | + stream-match-mask = <0x7C00>; |
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| 155 | + ... |
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| 156 | + }; |
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| 157 | + |
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| 158 | + gic: interrupt-controller@6000000 { |
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| 159 | + compatible = "arm,gic-v3"; |
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| 160 | + ... |
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| 161 | + } |
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| 162 | + its: gic-its@6020000 { |
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| 163 | + compatible = "arm,gic-v3-its"; |
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| 164 | + msi-controller; |
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| 165 | + ... |
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| 166 | + }; |
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93 | 167 | |
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94 | 168 | fsl_mc: fsl-mc@80c000000 { |
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95 | 169 | compatible = "fsl,qoriq-mc"; |
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96 | 170 | reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ |
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97 | 171 | <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ |
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98 | | - msi-parent = <&its>; |
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| 172 | + /* define map for ICIDs 23-64 */ |
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| 173 | + iommu-map = <23 &smmu 23 41>; |
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| 174 | + /* define msi map for ICIDs 23-64 */ |
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| 175 | + msi-map = <23 &its 23 41>; |
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99 | 176 | #address-cells = <3>; |
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100 | 177 | #size-cells = <1>; |
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101 | 178 | |
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