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| 81 | 81 | #define ADC_DIG_CLK_MASK (0xf << 4) |
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| 82 | 82 | #define ADC_DIG_CLK_SFT 4 |
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| 83 | 83 | #define ADC_DIG_CLK_DIS (0x0 << 4) |
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| 84 | | -#define ADC_DIG_CLK_EN (0xf << 4) |
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| 84 | +#define ADC_DIG_CLK_EN (0xe << 4) |
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| 85 | 85 | |
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| 86 | 86 | #define I2STX_CKE_EN (0x1 << 6) |
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| 87 | 87 | #define I2STX_CKE_DIS (0x0 << 6) |
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| .. | .. |
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| 89 | 89 | #define DAC_DIG_CLK_MASK (0xf << 0) |
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| 90 | 90 | #define DAC_DIG_CLK_SFT 0 |
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| 91 | 91 | #define DAC_DIG_CLK_DIS (0x0 << 0) |
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| 92 | | -#define DAC_DIG_CLK_EN (0xf << 0) |
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| 92 | +#define DAC_DIG_CLK_EN (0xe << 0) |
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| 93 | + |
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| 94 | +#define I2STX_EN_MASK BIT(4) |
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| 95 | +#define I2STX_EN BIT(4) |
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| 96 | +#define I2STX_DIS 0 |
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| 97 | + |
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| 98 | +#define I2SRX_EN_MASK BIT(0) |
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| 99 | +#define I2SRX_EN BIT(0) |
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| 100 | +#define I2SRX_DIS 0 |
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| 93 | 101 | |
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| 94 | 102 | /* RK817_CODEC_APLL_CFG5 */ |
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| 95 | 103 | #define PLL_PW_DOWN (0x01 << 0) |
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