export RK_PA3

hc

2024-02-19 151fecfb72a0d602dfe79790602ef64b4e241574

 kernel/include/uapi/linux/mdio.h
..
..
@@ -45,10 +45,14 @@
45
45
 #define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */
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 #define MDIO_AN_LPA		19	/* AN LP abilities (base page) */
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 #define MDIO_PCS_EEE_ABLE	20	/* EEE Capability register */
48
+#define MDIO_PCS_EEE_ABLE2	21	/* EEE Capability register 2 */
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+#define MDIO_PMA_NG_EXTABLE	21	/* 2.5G/5G PMA/PMD extended ability */
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 #define MDIO_PCS_EEE_WK_ERR	22	/* EEE wake error counter */
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 #define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */
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 #define MDIO_AN_EEE_ADV		60	/* EEE advertisement */
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 #define MDIO_AN_EEE_LPABLE	61	/* EEE link partner ability */
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+#define MDIO_AN_EEE_ADV2	62	/* EEE advertisement 2 */
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+#define MDIO_AN_EEE_LPABLE2	63	/* EEE link partner ability 2 */
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56
 
53
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 /* Media-dependent registers. */
54
58
 #define MDIO_PMA_10GBT_SWAPPOL	130	/* 10GBASE-T pair swap & polarity */
..
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@@ -92,6 +96,10 @@
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 #define MDIO_CTRL1_SPEED10G		(MDIO_CTRL1_SPEEDSELEXT | 0x00)
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 /* 10PASS-TS/2BASE-TL */
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 #define MDIO_CTRL1_SPEED10P2B		(MDIO_CTRL1_SPEEDSELEXT | 0x04)
99
+/* 2.5 Gb/s */
100
+#define MDIO_CTRL1_SPEED2_5G		(MDIO_CTRL1_SPEEDSELEXT | 0x18)
101
+/* 5 Gb/s */
102
+#define MDIO_CTRL1_SPEED5G		(MDIO_CTRL1_SPEEDSELEXT | 0x1c)
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103
 
96
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 /* Status register 1. */
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 #define MDIO_STAT1_LPOWERABLE		0x0002	/* Low-power ability */
..
..
@@ -115,6 +123,7 @@
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123
 
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 /* Device present registers. */
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 #define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
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+#define MDIO_DEVS_C22PRESENT		MDIO_DEVS_PRESENT(0)
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127
 #define MDIO_DEVS_PMAPMD		MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
119
128
 #define MDIO_DEVS_WIS			MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
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129
 #define MDIO_DEVS_PCS			MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
..
..
@@ -123,6 +132,8 @@
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 #define MDIO_DEVS_TC			MDIO_DEVS_PRESENT(MDIO_MMD_TC)
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 #define MDIO_DEVS_AN			MDIO_DEVS_PRESENT(MDIO_MMD_AN)
125
134
 #define MDIO_DEVS_C22EXT		MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
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+#define MDIO_DEVS_VEND1			MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
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+#define MDIO_DEVS_VEND2			MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
126
137
 
127
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 /* Control register 2. */
128
139
 #define MDIO_PMA_CTRL2_TYPE		0x000f	/* PMA/PMD type selection */
..
..
@@ -142,6 +153,8 @@
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 #define MDIO_PMA_CTRL2_1000BKX		0x000d	/* 1000BASE-KX type */
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 #define MDIO_PMA_CTRL2_100BTX		0x000e	/* 100BASE-TX type */
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 #define MDIO_PMA_CTRL2_10BT		0x000f	/* 10BASE-T type */
156
+#define MDIO_PMA_CTRL2_2_5GBT		0x0030  /* 2.5GBaseT type */
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+#define MDIO_PMA_CTRL2_5GBT		0x0031  /* 5GBaseT type */
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 #define MDIO_PCS_CTRL2_TYPE		0x0003	/* PCS type selection */
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 #define MDIO_PCS_CTRL2_10GBR		0x0000	/* 10GBASE-R type */
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 #define MDIO_PCS_CTRL2_10GBX		0x0001	/* 10GBASE-X type */
..
..
@@ -195,6 +208,7 @@
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 #define MDIO_PMA_EXTABLE_1000BKX	0x0040	/* 1000BASE-KX ability */
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 #define MDIO_PMA_EXTABLE_100BTX		0x0080	/* 100BASE-TX ability */
197
210
 #define MDIO_PMA_EXTABLE_10BT		0x0100	/* 10BASE-T ability */
211
+#define MDIO_PMA_EXTABLE_NBT		0x4000  /* 2.5/5GBASE-T ability */
198
212
 
199
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 /* PHY XGXS lane state register. */
200
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 #define MDIO_PHYXS_LNSTAT_SYNC0		0x0001
..
..
@@ -231,9 +245,13 @@
231
245
 #define MDIO_PCS_10GBRT_STAT2_BER	0x3f00
232
246
 
233
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 /* AN 10GBASE-T control register. */
248
+#define MDIO_AN_10GBT_CTRL_ADV2_5G	0x0080	/* Advertise 2.5GBASE-T */
249
+#define MDIO_AN_10GBT_CTRL_ADV5G	0x0100	/* Advertise 5GBASE-T */
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250
 #define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */
235
251
 
236
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 /* AN 10GBASE-T status register. */
253
+#define MDIO_AN_10GBT_STAT_LP2_5G	0x0020  /* LP is 2.5GBT capable */
254
+#define MDIO_AN_10GBT_STAT_LP5G		0x0040  /* LP is 5GBT capable */
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255
 #define MDIO_AN_10GBT_STAT_LPTRR	0x0200	/* LP training reset req. */
238
256
 #define MDIO_AN_10GBT_STAT_LPLTABLE	0x0400	/* LP loop timing ability */
239
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 #define MDIO_AN_10GBT_STAT_LP10G	0x0800	/* LP is 10GBT capable */
..
..
@@ -261,6 +279,17 @@
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 #define MDIO_EEE_1000KX		0x0010	/* 1000KX EEE cap */
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 #define MDIO_EEE_10GKX4		0x0020	/* 10G KX4 EEE cap */
263
281
 #define MDIO_EEE_10GKR		0x0040	/* 10G KR EEE cap */
282
+#define MDIO_EEE_40GR_FW	0x0100	/* 40G R fast wake */
283
+#define MDIO_EEE_40GR_DS	0x0200	/* 40G R deep sleep */
284
+#define MDIO_EEE_100GR_FW	0x1000	/* 100G R fast wake */
285
+#define MDIO_EEE_100GR_DS	0x2000	/* 100G R deep sleep */
286
+
287
+#define MDIO_EEE_2_5GT		0x0001	/* 2.5GT EEE cap */
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+#define MDIO_EEE_5GT		0x0002	/* 5GT EEE cap */
289
+
290
+/* 2.5G/5G Extended abilities register. */
291
+#define MDIO_PMA_NG_EXTABLE_2_5GBT	0x0001	/* 2.5GBASET ability */
292
+#define MDIO_PMA_NG_EXTABLE_5GBT	0x0002	/* 5GBASET ability */
264
293
 
265
294
 /* LASI RX_ALARM control/status registers. */
266
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 #define MDIO_PMA_LASI_RX_PHYXSLFLT	0x0001	/* PHY XS RX local fault */
..
..
@@ -295,4 +324,30 @@
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 	return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
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 }
297
326
 
327
+/* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
328
+#define MDIO_USXGMII_EEE_CLK_STP	0x0080	/* EEE clock stop supported */
329
+#define MDIO_USXGMII_EEE		0x0100	/* EEE supported */
330
+#define MDIO_USXGMII_SPD_MASK		0x0e00	/* USXGMII speed mask */
331
+#define MDIO_USXGMII_FULL_DUPLEX	0x1000	/* USXGMII full duplex */
332
+#define MDIO_USXGMII_DPX_SPD_MASK	0x1e00	/* USXGMII duplex and speed bits */
333
+#define MDIO_USXGMII_10			0x0000	/* 10Mbps */
334
+#define MDIO_USXGMII_10HALF		0x0000	/* 10Mbps half-duplex */
335
+#define MDIO_USXGMII_10FULL		0x1000	/* 10Mbps full-duplex */
336
+#define MDIO_USXGMII_100		0x0200	/* 100Mbps */
337
+#define MDIO_USXGMII_100HALF		0x0200	/* 100Mbps half-duplex */
338
+#define MDIO_USXGMII_100FULL		0x1200	/* 100Mbps full-duplex */
339
+#define MDIO_USXGMII_1000		0x0400	/* 1000Mbps */
340
+#define MDIO_USXGMII_1000HALF		0x0400	/* 1000Mbps half-duplex */
341
+#define MDIO_USXGMII_1000FULL		0x1400	/* 1000Mbps full-duplex */
342
+#define MDIO_USXGMII_10G		0x0600	/* 10Gbps */
343
+#define MDIO_USXGMII_10GHALF		0x0600	/* 10Gbps half-duplex */
344
+#define MDIO_USXGMII_10GFULL		0x1600	/* 10Gbps full-duplex */
345
+#define MDIO_USXGMII_2500		0x0800	/* 2500Mbps */
346
+#define MDIO_USXGMII_2500HALF		0x0800	/* 2500Mbps half-duplex */
347
+#define MDIO_USXGMII_2500FULL		0x1800	/* 2500Mbps full-duplex */
348
+#define MDIO_USXGMII_5000		0x0a00	/* 5000Mbps */
349
+#define MDIO_USXGMII_5000HALF		0x0a00	/* 5000Mbps half-duplex */
350
+#define MDIO_USXGMII_5000FULL		0x1a00	/* 5000Mbps full-duplex */
351
+#define MDIO_USXGMII_LINK		0x8000	/* PHY link with copper-side partner */
352
+
298
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 #endif /* _UAPI__LINUX_MDIO_H__ */