~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,9 +1,8 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* AD9523 SPI Low Jitter Clock Generator
3	4	*
4	5	* Copyright 2012 Analog Devices Inc.
5		- *
6		- * Licensed under the GPL-2.
7	6	*/
8	7
9	8	#ifndef IIO_FREQUENCY_AD9523_H_
..	..	@@ -129,8 +128,8 @@
129	128	* @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
130	129	* @pll2_freq_doubler_en: PLL2 frequency doubler enable.
131	130	* @pll2_r2_div: PLL2 R2 divider, range 0..31.
132		- * @pll2_vco_diff_m1: VCO1 divider, range 3..5.
133		- * @pll2_vco_diff_m2: VCO2 divider, range 3..5.
	131	+ * @pll2_vco_div_m1: VCO1 divider, range 3..5.
	132	+ * @pll2_vco_div_m2: VCO2 divider, range 3..5.
134	133	* @rpole2: PLL2 loop filter Rpole resistor value.
135	134	* @rzero: PLL2 loop filter Rzero resistor value.
136	135	* @cpole1: PLL2 loop filter Cpole capacitor value.
..	..	@@ -176,8 +175,8 @@
176	175	unsigned char pll2_ndiv_b_cnt;
177	176	bool pll2_freq_doubler_en;
178	177	unsigned char pll2_r2_div;
179		- unsigned char pll2_vco_diff_m1; /* 3..5 */
180		- unsigned char pll2_vco_diff_m2; /* 3..5 */
	178	+ unsigned char pll2_vco_div_m1; /* 3..5 */
	179	+ unsigned char pll2_vco_div_m2; /* 3..5 */
181	180
182	181	/* Loop Filter PLL2 */
183	182	enum rpole2_resistor rpole2;