export RK_PA3

hc

2024-02-19 151fecfb72a0d602dfe79790602ef64b4e241574

 kernel/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
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@@ -1,14 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/clk.h>
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@@ -156,7 +148,7 @@
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 		if (rate <= lpfr_lut[i].vco_rate)
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 			break;
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 	if (i == LPFR_LUT_SIZE) {
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-		dev_err(dev, "unable to get loop filter resistance. vco=%lu\n",
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+		DRM_DEV_ERROR(dev, "unable to get loop filter resistance. vco=%lu\n",
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 				rate);
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 		return -EINVAL;
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 	}
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@@ -386,7 +378,7 @@
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 	}
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 	if (unlikely(!locked))
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-		dev_err(dev, "DSI PLL lock failed\n");
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+		DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
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 	else
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 		DBG("DSI PLL Lock success");
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@@ -429,7 +421,7 @@
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 	locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
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 	if (unlikely(!locked))
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-		dev_err(dev, "DSI PLL lock failed\n");
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+		DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
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 	else
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 		DBG("DSI PLL lock success");
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@@ -468,7 +460,7 @@
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 	ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
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 					cached_state->vco_rate, 0);
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 	if (ret) {
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-		dev_err(&pll_28nm->pdev->dev,
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+		DRM_DEV_ERROR(&pll_28nm->pdev->dev,
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 			"restore vco rate failed. ret=%d\n", ret);
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 		return ret;
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 	}
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@@ -562,9 +554,9 @@
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 	snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
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 	snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
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 	clks[num++] = clk_register_mux(dev, clk_name,
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-			(const char *[]){
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+			((const char *[]){
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 				parent1, parent2
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-			}, 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +
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+			}), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +
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 			REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
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 	snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
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@@ -581,7 +573,7 @@
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 	ret = of_clk_add_provider(dev->of_node,
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 			of_clk_src_onecell_get, &pll_28nm->clk_data);
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 	if (ret) {
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-		dev_err(dev, "failed to register clk provider: %d\n", ret);
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+		DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
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 		return ret;
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 	}
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579
 
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@@ -607,7 +599,7 @@
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 	pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
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 	if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
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-		dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
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+		DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
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 		return ERR_PTR(-ENOMEM);
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 	}
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@@ -633,13 +625,13 @@
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 		pll->en_seq_cnt = 1;
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 		pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp;
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 	} else {
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-		dev_err(&pdev->dev, "phy type (%d) is not 28nm\n", type);
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+		DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type);
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 		return ERR_PTR(-EINVAL);
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 	}
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 	ret = pll_28nm_register(pll_28nm);
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 	if (ret) {
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-		dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
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+		DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
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 		return ERR_PTR(ret);
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 	}
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