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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6 
 kernel/include/uapi/drm/amdgpu_drm.h
....@@ -125,9 +125,19 @@
125125 /* Flag that BO sharing will be explicitly synchronized */
126126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC		(1 << 7)
127127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
128
- * for the second page onward should be set to NC.
128
+ * for the second page onward should be set to NC. It should never
129
+ * be used by user space applications.
129130  */
130
-#define AMDGPU_GEM_CREATE_MQD_GFX9		(1 << 8)
131
+#define AMDGPU_GEM_CREATE_CP_MQD_GFX9		(1 << 8)
132
+/* Flag that BO may contain sensitive data that must be wiped before
133
+ * releasing the memory
134
+ */
135
+#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE	(1 << 9)
136
+/* Flag that BO will be encrypted and that the TMZ bit should be
137
+ * set in the PTEs when mapping this buffer via GPUVM or
138
+ * accessing it with various hw blocks
139
+ */
140
+#define AMDGPU_GEM_CREATE_ENCRYPTED		(1 << 10)
131141 
132142 struct drm_amdgpu_gem_create_in  {
133143 	/** the requested memory size */
....@@ -210,13 +220,19 @@
210220 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
211221 /* indicate some job from this context once cause gpu hang */
212222 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
223
+/* indicate some errors are detected by RAS */
224
+#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE   (1<<3)
225
+#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE   (1<<4)
213226 
214227 /* Context priority level */
215228 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
216229 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
217230 #define AMDGPU_CTX_PRIORITY_LOW         -512
218231 #define AMDGPU_CTX_PRIORITY_NORMAL      0
219
-/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
232
+/*
233
+ * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
234
+ * CAP_SYS_NICE or DRM_MASTER
235
+*/
220236 #define AMDGPU_CTX_PRIORITY_HIGH        512
221237 #define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
222238 
....@@ -226,6 +242,7 @@
226242 	/** For future use, no flags defined so far */
227243 	__u32	flags;
228244 	__u32	ctx_id;
245
+	/** AMDGPU_CTX_PRIORITY_* */
229246 	__s32	priority;
230247 };
231248 
....@@ -272,13 +289,15 @@
272289 
273290 /* sched ioctl */
274291 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE	1
292
+#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE	2
275293 
276294 struct drm_amdgpu_sched_in {
277295 	/* AMDGPU_SCHED_OP_* */
278296 	__u32	op;
279297 	__u32	fd;
298
+	/** AMDGPU_CTX_PRIORITY_* */
280299 	__s32	priority;
281
-	__u32	flags;
300
+	__u32   ctx_id;
282301 };
283302 
284303 union drm_amdgpu_sched {
....@@ -326,6 +345,16 @@
326345 /* GFX9 and later: */
327346 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
328347 #define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
348
+#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT		5
349
+#define AMDGPU_TILING_DCC_OFFSET_256B_MASK		0xFFFFFF
350
+#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT		29
351
+#define AMDGPU_TILING_DCC_PITCH_MAX_MASK		0x3FFF
352
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT		43
353
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK		0x1
354
+#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT	44
355
+#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK		0x1
356
+#define AMDGPU_TILING_SCANOUT_SHIFT			63
357
+#define AMDGPU_TILING_SCANOUT_MASK			0x1
329358 
330359 /* Set/Get helpers for tiling flags. */
331360 #define AMDGPU_TILING_SET(field, value) \
....@@ -473,14 +502,16 @@
473502 #define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
474503 /* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
475504 #define AMDGPU_VM_MTYPE_DEFAULT		(0 << 5)
476
-/* Use NC MTYPE instead of default MTYPE */
505
+/* Use Non Coherent MTYPE instead of default MTYPE */
477506 #define AMDGPU_VM_MTYPE_NC		(1 << 5)
478
-/* Use WC MTYPE instead of default MTYPE */
507
+/* Use Write Combine MTYPE instead of default MTYPE */
479508 #define AMDGPU_VM_MTYPE_WC		(2 << 5)
480
-/* Use CC MTYPE instead of default MTYPE */
509
+/* Use Cache Coherent MTYPE instead of default MTYPE */
481510 #define AMDGPU_VM_MTYPE_CC		(3 << 5)
482
-/* Use UC MTYPE instead of default MTYPE */
511
+/* Use UnCached MTYPE instead of default MTYPE */
483512 #define AMDGPU_VM_MTYPE_UC		(4 << 5)
513
+/* Use Read Write MTYPE instead of default MTYPE */
514
+#define AMDGPU_VM_MTYPE_RW		(5 << 5)
484515 
485516 struct drm_amdgpu_gem_va {
486517 	/** GEM object handle */
....@@ -517,6 +548,9 @@
517548 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
518549 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
519550 #define AMDGPU_CHUNK_ID_BO_HANDLES      0x06
551
+#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES	0x07
552
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x08
553
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x09
520554 
521555 struct drm_amdgpu_cs_chunk {
522556 	__u32		chunk_id;
....@@ -530,7 +564,7 @@
530564 	/**  Handle of resource list associated with CS */
531565 	__u32		bo_list_handle;
532566 	__u32		num_chunks;
533
-	__u32		_pad;
567
+	__u32		flags;
534568 	/** this points to __u64 * which point to cs chunks */
535569 	__u64		chunks;
536570 };
....@@ -558,6 +592,19 @@
558592 /* The IB fence should do the L2 writeback but not invalidate any shader
559593  * caches (L2/vL1/sL1/I$). */
560594 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
595
+
596
+/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
597
+ * This will reset wave ID counters for the IB.
598
+ */
599
+#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
600
+
601
+/* Flag the IB as secure (TMZ)
602
+ */
603
+#define AMDGPU_IB_FLAGS_SECURE  (1 << 5)
604
+
605
+/* Tell KMD to flush and invalidate caches
606
+ */
607
+#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC  (1 << 6)
561608 
562609 struct drm_amdgpu_cs_chunk_ib {
563610 	__u32 _pad;
....@@ -592,6 +639,12 @@
592639 	__u32 handle;
593640 };
594641 
642
+struct drm_amdgpu_cs_chunk_syncobj {
643
+       __u32 handle;
644
+       __u32 flags;
645
+       __u64 point;
646
+};
647
+
595648 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ	0
596649 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD	1
597650 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD	2
....@@ -620,6 +673,7 @@
620673  */
621674 #define AMDGPU_IDS_FLAGS_FUSION         0x1
622675 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
676
+#define AMDGPU_IDS_FLAGS_TMZ            0x4
623677 
624678 /* indicate if acceleration can be working */
625679 #define AMDGPU_INFO_ACCEL_WORKING		0x00
....@@ -665,6 +719,12 @@
665719 	#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
666720 	/* Subquery id: Query GFX RLC SRLS firmware version */
667721 	#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
722
+	/* Subquery id: Query DMCU firmware version */
723
+	#define AMDGPU_INFO_FW_DMCU		0x12
724
+	#define AMDGPU_INFO_FW_TA		0x13
725
+	/* Subquery id: Query DMCUB firmware version */
726
+	#define AMDGPU_INFO_FW_DMCUB		0x14
727
+
668728 /* number of bytes moved for TTM migration */
669729 #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
670730 /* the used VRAM size */
....@@ -718,6 +778,37 @@
718778 /* Number of VRAM page faults on CPU access. */
719779 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E
720780 #define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
781
+/* query ras mask of enabled features*/
782
+#define AMDGPU_INFO_RAS_ENABLED_FEATURES	0x20
783
+
784
+/* RAS MASK: UMC (VRAM) */
785
+#define AMDGPU_INFO_RAS_ENABLED_UMC			(1 << 0)
786
+/* RAS MASK: SDMA */
787
+#define AMDGPU_INFO_RAS_ENABLED_SDMA			(1 << 1)
788
+/* RAS MASK: GFX */
789
+#define AMDGPU_INFO_RAS_ENABLED_GFX			(1 << 2)
790
+/* RAS MASK: MMHUB */
791
+#define AMDGPU_INFO_RAS_ENABLED_MMHUB			(1 << 3)
792
+/* RAS MASK: ATHUB */
793
+#define AMDGPU_INFO_RAS_ENABLED_ATHUB			(1 << 4)
794
+/* RAS MASK: PCIE */
795
+#define AMDGPU_INFO_RAS_ENABLED_PCIE			(1 << 5)
796
+/* RAS MASK: HDP */
797
+#define AMDGPU_INFO_RAS_ENABLED_HDP			(1 << 6)
798
+/* RAS MASK: XGMI */
799
+#define AMDGPU_INFO_RAS_ENABLED_XGMI			(1 << 7)
800
+/* RAS MASK: DF */
801
+#define AMDGPU_INFO_RAS_ENABLED_DF			(1 << 8)
802
+/* RAS MASK: SMN */
803
+#define AMDGPU_INFO_RAS_ENABLED_SMN			(1 << 9)
804
+/* RAS MASK: SEM */
805
+#define AMDGPU_INFO_RAS_ENABLED_SEM			(1 << 10)
806
+/* RAS MASK: MP0 */
807
+#define AMDGPU_INFO_RAS_ENABLED_MP0			(1 << 11)
808
+/* RAS MASK: MP1 */
809
+#define AMDGPU_INFO_RAS_ENABLED_MP1			(1 << 12)
810
+/* RAS MASK: FUSE */
811
+#define AMDGPU_INFO_RAS_ENABLED_FUSE			(1 << 13)
721812 
722813 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
723814 #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
....@@ -854,6 +945,7 @@
854945 #define AMDGPU_VRAM_TYPE_HBM   6
855946 #define AMDGPU_VRAM_TYPE_DDR3  7
856947 #define AMDGPU_VRAM_TYPE_DDR4  8
948
+#define AMDGPU_VRAM_TYPE_GDDR6 9
857949 
858950 struct drm_amdgpu_info_device {
859951 	/** PCI Device ID */
....@@ -933,6 +1025,10 @@
9331025 	__u64 high_va_offset;
9341026 	/** The maximum high virtual address */
9351027 	__u64 high_va_max;
1028
+	/* gfx10 pa_sc_tile_steering_override */
1029
+	__u32 pa_sc_tile_steering_override;
1030
+	/* disabled TCCs */
1031
+	__u64 tcc_disabled_mask;
9361032 };
9371033 
9381034 struct drm_amdgpu_info_hw_ip {
....@@ -986,6 +1082,7 @@
9861082 #define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
9871083 #define AMDGPU_FAMILY_AI			141 /* Vega10 */
9881084 #define AMDGPU_FAMILY_RV			142 /* Raven */
1085
+#define AMDGPU_FAMILY_NV			143 /* Navi10 */
9891086 
9901087 #if defined(__cplusplus)
9911088 }