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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6

 kernel/arch/powerpc/kernel/fpu.S
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  *  FPU support code, moved here from head.S so that it can be used
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  *  by chips which use other head-whatever.S files.
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@@ -6,18 +7,11 @@
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  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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  *    Copyright (C) 1996 Paul Mackerras.
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  *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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- *
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- *  This program is free software; you can redistribute it and/or
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- *  modify it under the terms of the GNU General Public License
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- *  as published by the Free Software Foundation; either version
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- *  2 of the License, or (at your option) any later version.
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- *
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  */
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 #include <asm/reg.h>
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 #include <asm/page.h>
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 #include <asm/mmu.h>
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-#include <asm/pgtable.h>
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 #include <asm/cputable.h>
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 #include <asm/cache.h>
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 #include <asm/thread_info.h>
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@@ -63,6 +57,7 @@
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 	REST_32FPVSRS(0, R4, R3)
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 	blr
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 EXPORT_SYMBOL(load_fp_state)
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+_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */
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 /*
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  * Store FP state into memory, including FPSCR
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@@ -92,12 +87,14 @@
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 	oris	r5,r5,MSR_VSX@h
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 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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 #endif
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-	SYNC
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 	MTMSRD(r5)			/* enable use of fpu now */
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 	isync
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 	/* enable use of FP after return */
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 #ifdef CONFIG_PPC32
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 	mfspr	r5,SPRN_SPRG_THREAD	/* current task's THREAD (phys) */
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+#ifdef CONFIG_VMAP_STACK
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+	tovirt(r5, r5)
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+#endif
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 	lwz	r4,THREAD_FPEXC_MODE(r5)
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 	ori	r9,r9,MSR_FP		/* enable FP for current */
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 	or	r9,r9,r4
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@@ -109,9 +106,7 @@
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 	or	r12,r12,r4
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 	std	r12,_MSR(r1)
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 #endif
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-	/* Don't care if r4 overflows, this is desired behaviour */
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-	lbz	r4,THREAD_LOAD_FP(r5)
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-	addi	r4,r4,1
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+	li	r4,1
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 	stb	r4,THREAD_LOAD_FP(r5)
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 	addi	r10,r5,THREAD_FPSTATE
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 	lfd	fr0,FPSTATE_FPSCR(r10)
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@@ -120,6 +115,7 @@
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 	/* restore registers and return */
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 	/* we haven't used ctr or xer or lr */
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 	blr
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+_ASM_NOKPROBE_SYMBOL(load_up_fpu)
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 /*
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  * save_fpu(tsk)
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@@ -136,19 +132,4 @@
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 2:	SAVE_32FPVSRS(0, R4, R6)
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 	mffs	fr0
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 	stfd	fr0,FPSTATE_FPSCR(r6)
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-	blr
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-
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-/*
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- * These are used in the alignment trap handler when emulating
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- * single-precision loads and stores.
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- */
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-
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-_GLOBAL(cvt_fd)
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-	lfs	0,0(r3)
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-	stfd	0,0(r4)
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-	blr
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-
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-_GLOBAL(cvt_df)
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-	lfd	0,0(r3)
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-	stfs	0,0(r4)
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 	blr