hc
2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6
kernel/arch/mips/lib/memset.S
....@@ -78,7 +78,6 @@
7878 #endif
7979 .endm
8080
81
- .set noreorder
8281 .align 5
8382
8483 /*
....@@ -94,13 +93,16 @@
9493 .endif
9594
9695 sltiu t0, a2, STORSIZE /* very small region? */
96
+ .set noreorder
9797 bnez t0, .Lsmall_memset\@
9898 andi t0, a0, STORMASK /* aligned? */
99
+ .set reorder
99100
100101 #ifdef CONFIG_CPU_MICROMIPS
101102 move t8, a1 /* used by 'swp' instruction */
102103 move t9, a1
103104 #endif
105
+ .set noreorder
104106 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
105107 beqz t0, 1f
106108 PTR_SUBU t0, STORSIZE /* alignment in bytes */
....@@ -111,8 +113,9 @@
111113 PTR_SUBU t0, AT /* alignment in bytes */
112114 .set at
113115 #endif
116
+ .set reorder
114117
115
-#ifndef CONFIG_CPU_MIPSR6
118
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
116119 R10KCBARRIER(0(ra))
117120 #ifdef __MIPSEB__
118121 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
....@@ -122,11 +125,13 @@
122125 PTR_SUBU a0, t0 /* long align ptr */
123126 PTR_ADDU a2, t0 /* correct size */
124127
125
-#else /* CONFIG_CPU_MIPSR6 */
128
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
126129 #define STORE_BYTE(N) \
127130 EX(sb, a1, N(a0), .Lbyte_fixup\@); \
131
+ .set noreorder; \
128132 beqz t0, 0f; \
129
- PTR_ADDU t0, 1;
133
+ PTR_ADDU t0, 1; \
134
+ .set reorder;
130135
131136 PTR_ADDU a2, t0 /* correct size */
132137 PTR_ADDU t0, 1
....@@ -145,19 +150,17 @@
145150 ori a0, STORMASK
146151 xori a0, STORMASK
147152 PTR_ADDIU a0, STORSIZE
148
-#endif /* CONFIG_CPU_MIPSR6 */
153
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
149154 1: ori t1, a2, 0x3f /* # of full blocks */
150155 xori t1, 0x3f
156
+ andi t0, a2, 0x40-STORSIZE
151157 beqz t1, .Lmemset_partial\@ /* no block to fill */
152
- andi t0, a2, 0x40-STORSIZE
153158
154159 PTR_ADDU t1, a0 /* end address */
155
- .set reorder
156160 1: PTR_ADDIU a0, 64
157161 R10KCBARRIER(0(ra))
158162 f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
159163 bne t1, a0, 1b
160
- .set noreorder
161164
162165 .Lmemset_partial\@:
163166 R10KCBARRIER(0(ra))
....@@ -173,28 +176,27 @@
173176 PTR_SUBU t1, AT
174177 .set at
175178 #endif
179
+ PTR_ADDU a0, t0 /* dest ptr */
176180 jr t1
177
- PTR_ADDU a0, t0 /* dest ptr */
178181
179
- .set push
180
- .set noreorder
181
- .set nomacro
182182 /* ... but first do longs ... */
183183 f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
184
-2: .set pop
185
- andi a2, STORMASK /* At most one long to go */
184
+2: andi a2, STORMASK /* At most one long to go */
186185
186
+ .set noreorder
187187 beqz a2, 1f
188
-#ifndef CONFIG_CPU_MIPSR6
188
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
189189 PTR_ADDU a0, a2 /* What's left */
190
+ .set reorder
190191 R10KCBARRIER(0(ra))
191192 #ifdef __MIPSEB__
192193 EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
193194 #else
194195 EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
195196 #endif
196
-#else
197
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
197198 PTR_SUBU t0, $0, a2
199
+ .set reorder
198200 move a2, zero /* No remaining longs */
199201 PTR_ADDIU t0, 1
200202 STORE_BYTE(0)
....@@ -209,42 +211,43 @@
209211 EX(sb, a1, 6(a0), .Lbyte_fixup\@)
210212 #endif
211213 0:
212
-#endif
213
-1: jr ra
214
- move a2, zero
214
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
215
+1: move a2, zero
216
+ jr ra
215217
216218 .Lsmall_memset\@:
219
+ PTR_ADDU t1, a0, a2
217220 beqz a2, 2f
218
- PTR_ADDU t1, a0, a2
219221
220222 1: PTR_ADDIU a0, 1 /* fill bytewise */
221223 R10KCBARRIER(0(ra))
224
+ .set noreorder
222225 bne t1, a0, 1b
223226 EX(sb, a1, -1(a0), .Lsmall_fixup\@)
227
+ .set reorder
224228
225
-2: jr ra /* done */
226
- move a2, zero
229
+2: move a2, zero
230
+ jr ra /* done */
227231 .if __memset == 1
228232 END(memset)
229233 .set __memset, 0
230234 .hidden __memset
231235 .endif
232236
233
-#ifdef CONFIG_CPU_MIPSR6
237
+#ifdef CONFIG_CPU_NO_LOAD_STORE_LR
234238 .Lbyte_fixup\@:
235239 /*
236240 * unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1
237241 * a2 = a2 - t0 + 1
238242 */
239243 PTR_SUBU a2, t0
244
+ PTR_ADDIU a2, 1
240245 jr ra
241
- PTR_ADDIU a2, 1
242
-#endif /* CONFIG_CPU_MIPSR6 */
246
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
243247
244248 .Lfirst_fixup\@:
245249 /* unset_bytes already in a2 */
246250 jr ra
247
- nop
248251
249252 .Lfwd_fixup\@:
250253 /*
....@@ -255,8 +258,8 @@
255258 andi a2, 0x3f
256259 LONG_L t0, THREAD_BUADDR(t0)
257260 LONG_ADDU a2, t1
261
+ LONG_SUBU a2, t0
258262 jr ra
259
- LONG_SUBU a2, t0
260263
261264 .Lpartial_fixup\@:
262265 /*
....@@ -267,24 +270,21 @@
267270 andi a2, STORMASK
268271 LONG_L t0, THREAD_BUADDR(t0)
269272 LONG_ADDU a2, a0
273
+ LONG_SUBU a2, t0
270274 jr ra
271
- LONG_SUBU a2, t0
272275
273276 .Llast_fixup\@:
274277 /* unset_bytes already in a2 */
275278 jr ra
276
- nop
277279
278280 .Lsmall_fixup\@:
279281 /*
280282 * unset_bytes = end_addr - current_addr + 1
281283 * a2 = t1 - a0 + 1
282284 */
283
- .set reorder
284285 PTR_SUBU a2, t1, a0
285286 PTR_ADDIU a2, 1
286287 jr ra
287
- .set noreorder
288288
289289 .endm
290290
....@@ -298,8 +298,8 @@
298298
299299 LEAF(memset)
300300 EXPORT_SYMBOL(memset)
301
+ move v0, a0 /* result */
301302 beqz a1, 1f
302
- move v0, a0 /* result */
303303
304304 andi a1, 0xff /* spread fillword */
305305 LONG_SLL t1, a1, 8