~hc/RK356X_SDK_RELEASE.git

..	..	@@ -2,37 +2,44 @@
2	2	config MIPS
3	3	bool
4	4	default y
5		- select ARCH_BINFMT_ELF_STATE
6		- select ARCH_CLOCKSOURCE_DATA
7		- select ARCH_DISCARD_MEMBLOCK
8		- select ARCH_HAS_ELF_RANDOMIZE
	5	+ select ARCH_32BIT_OFF_T if !64BIT
	6	+ select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
	7	+ select ARCH_HAS_CPU_FINALIZE_INIT
	8	+ select ARCH_HAS_FORTIFY_SOURCE
	9	+ select ARCH_HAS_KCOV
	10	+ select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
	11	+ select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
9	12	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
	13	+ select ARCH_HAS_UBSAN_SANITIZE_ALL
10	14	select ARCH_SUPPORTS_UPROBES
11	15	select ARCH_USE_BUILTIN_BSWAP
12	16	select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
13	17	select ARCH_USE_QUEUED_RWLOCKS
14	18	select ARCH_USE_QUEUED_SPINLOCKS
	19	+ select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
15	20	select ARCH_WANT_IPC_PARSE_VERSION
16		- select BUILDTIME_EXTABLE_SORT
	21	+ select BUILDTIME_TABLE_SORT
17	22	select CLONE_BACKWARDS
	23	+ select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
18	24	select CPU_PM if CPU_IDLE
19		- select DMA_DIRECT_OPS
20	25	select GENERIC_ATOMIC64 if !64BIT
21	26	select GENERIC_CLOCKEVENTS
22	27	select GENERIC_CMOS_UPDATE
23	28	select GENERIC_CPU_AUTOPROBE
24	29	select GENERIC_GETTIMEOFDAY
	30	+ select GENERIC_IOMAP
25	31	select GENERIC_IRQ_PROBE
26	32	select GENERIC_IRQ_SHOW
	33	+ select GENERIC_ISA_DMA if EISA
27	34	select GENERIC_LIB_ASHLDI3
28	35	select GENERIC_LIB_ASHRDI3
29	36	select GENERIC_LIB_CMPDI2
30	37	select GENERIC_LIB_LSHRDI3
31	38	select GENERIC_LIB_UCMPDI2
32		- select GENERIC_PCI_IOMAP
33	39	select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
34	40	select GENERIC_SMP_IDLE_THREAD
35	41	select GENERIC_TIME_VSYSCALL
	42	+ select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
36	43	select HANDLE_DOMAIN_IRQ
37	44	select HAVE_ARCH_COMPILER_H
38	45	select HAVE_ARCH_JUMP_LABEL
..	..	@@ -41,73 +48,100 @@
41	48	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
42	49	select HAVE_ARCH_SECCOMP_FILTER
43	50	select HAVE_ARCH_TRACEHOOK
44		- select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
45		- select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
46		- select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
	51	+ select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
	52	+ select HAVE_ASM_MODVERSIONS
	53	+ select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
47	54	select HAVE_CONTEXT_TRACKING
48		- select HAVE_COPY_THREAD_TLS
	55	+ select HAVE_TIF_NOHZ
49	56	select HAVE_C_RECORDMCOUNT
50	57	select HAVE_DEBUG_KMEMLEAK
51	58	select HAVE_DEBUG_STACKOVERFLOW
52	59	select HAVE_DMA_CONTIGUOUS
53	60	select HAVE_DYNAMIC_FTRACE
	61	+ select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
54	62	select HAVE_EXIT_THREAD
	63	+ select HAVE_FAST_GUP
55	64	select HAVE_FTRACE_MCOUNT_RECORD
56	65	select HAVE_FUNCTION_GRAPH_TRACER
57	66	select HAVE_FUNCTION_TRACER
58		- select HAVE_GENERIC_DMA_COHERENT
	67	+ select HAVE_GCC_PLUGINS
	68	+ select HAVE_GENERIC_VDSO
59	69	select HAVE_IDE
	70	+ select HAVE_IOREMAP_PROT
60	71	select HAVE_IRQ_EXIT_ON_IRQ_STACK
61	72	select HAVE_IRQ_TIME_ACCOUNTING
62	73	select HAVE_KPROBES
63	74	select HAVE_KRETPROBES
64		- select HAVE_MEMBLOCK
65		- select HAVE_MEMBLOCK_NODE_MAP
	75	+ select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
66	76	select HAVE_MOD_ARCH_SPECIFIC
67	77	select HAVE_NMI
68	78	select HAVE_OPROFILE
69	79	select HAVE_PERF_EVENTS
70	80	select HAVE_REGS_AND_STACK_ACCESS_API
71	81	select HAVE_RSEQ
	82	+ select HAVE_SPARSE_SYSCALL_NR
72	83	select HAVE_STACKPROTECTOR
73	84	select HAVE_SYSCALL_TRACEPOINTS
74	85	select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT \|\| !SMP
75		- select HAVE_GENERIC_VDSO
76	86	select IRQ_FORCED_THREADING
77		- select MODULES_USE_ELF_RELA if MODULES && 64BIT
	87	+ select ISA if EISA
78	88	select MODULES_USE_ELF_REL if MODULES
	89	+ select MODULES_USE_ELF_RELA if MODULES && 64BIT
79	90	select PERF_USE_VMALLOC
80		- select RTC_LIB if !MACH_LOONGSON64
	91	+ select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
	92	+ select RTC_LIB
	93	+ select SET_FS
81	94	select SYSCTL_EXCEPTION_TRACE
82	95	select VIRT_TO_BUS
	96	+
	97	+config MIPS_FIXUP_BIGPHYS_ADDR
	98	+ bool
	99	+
	100	+config MIPS_GENERIC
	101	+ bool
	102	+
	103	+config MACH_INGENIC
	104	+ bool
	105	+ select SYS_SUPPORTS_32BIT_KERNEL
	106	+ select SYS_SUPPORTS_LITTLE_ENDIAN
	107	+ select SYS_SUPPORTS_ZBOOT
	108	+ select DMA_NONCOHERENT
	109	+ select IRQ_MIPS_CPU
	110	+ select PINCTRL
	111	+ select GPIOLIB
	112	+ select COMMON_CLK
	113	+ select GENERIC_IRQ_CHIP
	114	+ select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
	115	+ select USE_OF
	116	+ select CPU_SUPPORTS_CPUFREQ
	117	+ select MIPS_EXTERNAL_TIMER
83	118
84	119	menu "Machine selection"
85	120
86	121	choice
87	122	prompt "System type"
88		- default MIPS_GENERIC
	123	+ default MIPS_GENERIC_KERNEL
89	124
90		-config MIPS_GENERIC
	125	+config MIPS_GENERIC_KERNEL
91	126	bool "Generic board-agnostic MIPS kernel"
	127	+ select MIPS_GENERIC
92	128	select BOOT_RAW
93	129	select BUILTIN_DTB
94	130	select CEVT_R4K
95	131	select CLKSRC_MIPS_GIC
96	132	select COMMON_CLK
97		- select CPU_MIPSR2_IRQ_VI
98	133	select CPU_MIPSR2_IRQ_EI
	134	+ select CPU_MIPSR2_IRQ_VI
99	135	select CSRC_R4K
100	136	select DMA_PERDEV_COHERENT
101		- select HW_HAS_PCI
	137	+ select HAVE_PCI
102	138	select IRQ_MIPS_CPU
103		- select LIBFDT
104	139	select MIPS_AUTO_PFN_OFFSET
105	140	select MIPS_CPU_SCACHE
106	141	select MIPS_GIC
107	142	select MIPS_L1_CACHE_SHIFT_7
108	143	select NO_EXCEPT_FILL
109	144	select PCI_DRIVERS_GENERIC
110		- select PINCTRL
111	145	select SMP_UP if SMP
112	146	select SWAP_IO_SPACE
113	147	select SYS_HAS_CPU_MIPS32_R1
..	..	@@ -122,11 +156,13 @@
122	156	select SYS_SUPPORTS_HIGHMEM
123	157	select SYS_SUPPORTS_LITTLE_ENDIAN
124	158	select SYS_SUPPORTS_MICROMIPS
125		- select SYS_SUPPORTS_MIPS_CPS
126	159	select SYS_SUPPORTS_MIPS16
	160	+ select SYS_SUPPORTS_MIPS_CPS
127	161	select SYS_SUPPORTS_MULTITHREADING
128	162	select SYS_SUPPORTS_RELOCATABLE
129	163	select SYS_SUPPORTS_SMARTMIPS
	164	+ select SYS_SUPPORTS_ZBOOT
	165	+ select UHI_BOOT
130	166	select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
131	167	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
132	168	select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
..	..	@@ -147,6 +183,7 @@
147	183	select CSRC_R4K
148	184	select IRQ_MIPS_CPU
149	185	select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
	186	+ select MIPS_FIXUP_BIGPHYS_ADDR if PCI
150	187	select SYS_HAS_CPU_MIPS32_R1
151	188	select SYS_SUPPORTS_32BIT_KERNEL
152	189	select SYS_SUPPORTS_APM_EMULATION
..	..	@@ -171,7 +208,7 @@
171	208	select SYS_SUPPORTS_ZBOOT_UART16550
172	209	select GPIOLIB
173	210	select VLYNQ
174		- select HAVE_CLK
	211	+ select HAVE_LEGACY_CLK
175	212	help
176	213	Support for the Texas Instruments AR7 System-on-a-Chip
177	214	family: TNETD7100, 7200 and 7300.
..	..	@@ -199,11 +236,8 @@
199	236	select DMA_NONCOHERENT
200	237	select GPIOLIB
201	238	select PINCTRL
202		- select HAVE_CLK
203	239	select COMMON_CLK
204		- select CLKDEV_LOOKUP
205	240	select IRQ_MIPS_CPU
206		- select MIPS_MACHINE
207	241	select SYS_HAS_CPU_MIPS32_R2
208	242	select SYS_HAS_EARLY_PRINTK
209	243	select SYS_SUPPORTS_32BIT_KERNEL
..	..	@@ -258,7 +292,7 @@
258	292	select CEVT_R4K
259	293	select CSRC_R4K
260	294	select DMA_NONCOHERENT
261		- select HW_HAS_PCI
	295	+ select HAVE_PCI
262	296	select IRQ_MIPS_CPU
263	297	select SYS_HAS_CPU_MIPS32_R1
264	298	select NO_EXCEPT_FILL
..	..	@@ -274,7 +308,7 @@
274	308	select BCM47XX_SPROM
275	309	select BCM47XX_SSB if !BCM47XX_BCMA
276	310	help
277		- Support for BCM47XX based boards
	311	+ Support for BCM47XX based boards
278	312
279	313	config BCM63XX
280	314	bool "Broadcom BCM63XX based boards"
..	..	@@ -292,11 +326,11 @@
292	326	select SYS_HAS_CPU_BMIPS4380
293	327	select SWAP_IO_SPACE
294	328	select GPIOLIB
295		- select HAVE_CLK
296	329	select MIPS_L1_CACHE_SHIFT_4
297	330	select CLKDEV_LOOKUP
	331	+ select HAVE_LEGACY_CLK
298	332	help
299		- Support for BCM63XX based boards
	333	+ Support for BCM63XX based boards
300	334
301	335	config MIPS_COBALT
302	336	bool "Cobalt Server"
..	..	@@ -304,13 +338,12 @@
304	338	select CSRC_R4K
305	339	select CEVT_GT641XX
306	340	select DMA_NONCOHERENT
307		- select HW_HAS_PCI
	341	+ select FORCE_PCI
308	342	select I8253
309	343	select I8259
310	344	select IRQ_MIPS_CPU
311	345	select IRQ_GT641XX
312	346	select PCI_GT64XXX_PCI0
313		- select PCI
314	347	select SYS_HAS_CPU_NEVADA
315	348	select SYS_HAS_EARLY_PRINTK
316	349	select SYS_SUPPORTS_32BIT_KERNEL
..	..	@@ -357,8 +390,11 @@
357	390
358	391	config MACH_JAZZ
359	392	bool "Jazz family of machines"
	393	+ select ARC_MEMORY
	394	+ select ARC_PROMLIB
360	395	select ARCH_MIGHT_HAVE_PC_PARPORT
361	396	select ARCH_MIGHT_HAVE_PC_SERIO
	397	+ select DMA_OPS
362	398	select FW_ARC
363	399	select FW_ARC32
364	400	select ARCH_MAY_HAVE_PC_FDC
..	..	@@ -376,25 +412,18 @@
376	412	select SYS_SUPPORTS_64BIT_KERNEL
377	413	select SYS_SUPPORTS_100HZ
378	414	help
379		- This a family of machines based on the MIPS R4030 chipset which was
380		- used by several vendors to build RISC/os and Windows NT workstations.
381		- Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
382		- Olivetti M700-10 workstations.
	415	+ This a family of machines based on the MIPS R4030 chipset which was
	416	+ used by several vendors to build RISC/os and Windows NT workstations.
	417	+ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
	418	+ Olivetti M700-10 workstations.
383	419
384		-config MACH_INGENIC
	420	+config MACH_INGENIC_SOC
385	421	bool "Ingenic SoC based machines"
386		- select SYS_SUPPORTS_32BIT_KERNEL
387		- select SYS_SUPPORTS_LITTLE_ENDIAN
	422	+ select MIPS_GENERIC
	423	+ select MACH_INGENIC
388	424	select SYS_SUPPORTS_ZBOOT_UART16550
389		- select DMA_NONCOHERENT
390		- select IRQ_MIPS_CPU
391		- select PINCTRL
392		- select GPIOLIB
393		- select COMMON_CLK
394		- select GENERIC_IRQ_CHIP
395		- select BUILTIN_DTB
396		- select USE_OF
397		- select LIBFDT
	425	+ select CPU_SUPPORTS_CPUFREQ
	426	+ select MIPS_EXTERNAL_TIMER
398	427
399	428	config LANTIQ
400	429	bool "Lantiq based platforms"
..	..	@@ -414,31 +443,15 @@
414	443	select SWAP_IO_SPACE
415	444	select BOOT_RAW
416	445	select CLKDEV_LOOKUP
	446	+ select HAVE_LEGACY_CLK
417	447	select USE_OF
418	448	select PINCTRL
419	449	select PINCTRL_LANTIQ
420	450	select ARCH_HAS_RESET_CONTROLLER
421	451	select RESET_CONTROLLER
422	452
423		-config LASAT
424		- bool "LASAT Networks platforms"
425		- select CEVT_R4K
426		- select CRC32
427		- select CSRC_R4K
428		- select DMA_NONCOHERENT
429		- select SYS_HAS_EARLY_PRINTK
430		- select HW_HAS_PCI
431		- select IRQ_MIPS_CPU
432		- select PCI_GT64XXX_PCI0
433		- select MIPS_NILE4
434		- select R5000_CPU_SCACHE
435		- select SYS_HAS_CPU_R5000
436		- select SYS_SUPPORTS_32BIT_KERNEL
437		- select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
438		- select SYS_SUPPORTS_LITTLE_ENDIAN
439		-
440	453	config MACH_LOONGSON32
441		- bool "Loongson-1 family of machines"
	454	+ bool "Loongson 32-bit family of machines"
442	455	select SYS_SUPPORTS_ZBOOT
443	456	help
444	457	This enables support for the Loongson-1 family of machines.
..	..	@@ -447,18 +460,54 @@
447	460	the Institute of Computing Technology (ICT), Chinese Academy of
448	461	Sciences (CAS).
449	462
450		-config MACH_LOONGSON64
451		- bool "Loongson-2/3 family of machines"
	463	+config MACH_LOONGSON2EF
	464	+ bool "Loongson-2E/F family of machines"
452	465	select SYS_SUPPORTS_ZBOOT
	466	+ help
	467	+ This enables the support of early Loongson-2E/F family of machines.
	468	+
	469	+config MACH_LOONGSON64
	470	+ bool "Loongson 64-bit family of machines"
	471	+ select ARCH_SPARSEMEM_ENABLE
	472	+ select ARCH_MIGHT_HAVE_PC_PARPORT
	473	+ select ARCH_MIGHT_HAVE_PC_SERIO
	474	+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
	475	+ select BOOT_ELF32
	476	+ select BOARD_SCACHE
	477	+ select CSRC_R4K
	478	+ select CEVT_R4K
	479	+ select CPU_HAS_WB
	480	+ select FORCE_PCI
	481	+ select ISA
	482	+ select I8259
	483	+ select IRQ_MIPS_CPU
	484	+ select NO_EXCEPT_FILL
	485	+ select NR_CPUS_DEFAULT_64
	486	+ select USE_GENERIC_EARLY_PRINTK_8250
	487	+ select PCI_DRIVERS_GENERIC
	488	+ select SYS_HAS_CPU_LOONGSON64
	489	+ select SYS_HAS_EARLY_PRINTK
	490	+ select SYS_SUPPORTS_SMP
	491	+ select SYS_SUPPORTS_HOTPLUG_CPU
	492	+ select SYS_SUPPORTS_NUMA
	493	+ select SYS_SUPPORTS_64BIT_KERNEL
	494	+ select SYS_SUPPORTS_HIGHMEM
	495	+ select SYS_SUPPORTS_LITTLE_ENDIAN
	496	+ select SYS_SUPPORTS_ZBOOT
	497	+ select ZONE_DMA32
	498	+ select NUMA
	499	+ select SMP
	500	+ select COMMON_CLK
	501	+ select USE_OF
	502	+ select BUILTIN_DTB
	503	+ select PCI_HOST_GENERIC
453	504	help
454	505	This enables the support of Loongson-2/3 family of machines.
455	506
456		- Loongson-2 is a family of single-core CPUs and Loongson-3 is a
457		- family of multi-core CPUs. They are both 64-bit general-purpose
458		- MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
459		- of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
460		- in the People's Republic of China. The chief architect is Professor
461		- Weiwu Hu.
	507	+ Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
	508	+ GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
	509	+ and Loongson-2F which will be removed), developed by the Institute
	510	+ of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
462	511
463	512	config MACH_PISTACHIO
464	513	bool "IMG Pistachio SoC based boards"
..	..	@@ -471,7 +520,6 @@
471	520	select DMA_NONCOHERENT
472	521	select GPIOLIB
473	522	select IRQ_MIPS_CPU
474		- select LIBFDT
475	523	select MFD_SYSCON
476	524	select MIPS_CPU_SCACHE
477	525	select MIPS_GIC
..	..	@@ -499,22 +547,22 @@
499	547	select BOOT_RAW
500	548	select BUILTIN_DTB
501	549	select CEVT_R4K
502		- select CSRC_R4K
503	550	select CLKSRC_MIPS_GIC
504	551	select COMMON_CLK
	552	+ select CSRC_R4K
505	553	select DMA_MAYBE_COHERENT
506	554	select GENERIC_ISA_DMA
507	555	select HAVE_PCSPKR_PLATFORM
508		- select IRQ_MIPS_CPU
509		- select MIPS_GIC
510		- select HW_HAS_PCI
	556	+ select HAVE_PCI
511	557	select I8253
512	558	select I8259
	559	+ select IRQ_MIPS_CPU
513	560	select MIPS_BONITO64
514	561	select MIPS_CPU_SCACHE
	562	+ select MIPS_GIC
515	563	select MIPS_L1_CACHE_SHIFT_6
516		- select PCI_GT64XXX_PCI0
517	564	select MIPS_MSC
	565	+ select PCI_GT64XXX_PCI0
518	566	select SMP_UP if SMP
519	567	select SWAP_IO_SPACE
520	568	select SYS_HAS_CPU_MIPS32_R1
..	..	@@ -533,19 +581,17 @@
533	581	select SYS_SUPPORTS_HIGHMEM
534	582	select SYS_SUPPORTS_LITTLE_ENDIAN
535	583	select SYS_SUPPORTS_MICROMIPS
	584	+ select SYS_SUPPORTS_MIPS16
536	585	select SYS_SUPPORTS_MIPS_CMP
537	586	select SYS_SUPPORTS_MIPS_CPS
538		- select SYS_SUPPORTS_MIPS16
539	587	select SYS_SUPPORTS_MULTITHREADING
	588	+ select SYS_SUPPORTS_RELOCATABLE
540	589	select SYS_SUPPORTS_SMARTMIPS
541	590	select SYS_SUPPORTS_VPE_LOADER
542	591	select SYS_SUPPORTS_ZBOOT
543		- select SYS_SUPPORTS_RELOCATABLE
544	592	select USE_OF
545		- select LIBFDT
	593	+ select WAR_ICACHE_REFILLS
546	594	select ZONE_DMA32 if 64BIT
547		- select BUILTIN_DTB
548		- select LIBFDT
549	595	help
550	596	This enables support for the MIPS Technologies Malta evaluation
551	597	board.
..	..	@@ -558,13 +604,6 @@
558	604	Microchip PIC32 is a family of general-purpose 32 bit MIPS core
559	605	microcontrollers.
560	606
561		-config NEC_MARKEINS
562		- bool "NEC EMMA2RH Mark-eins board"
563		- select SOC_EMMA2RH
564		- select HW_HAS_PCI
565		- help
566		- This enables support for the NEC Electronics Mark-eins boards.
567		-
568	607	config MACH_VR41XX
569	608	bool "NEC VR4100 series based machines"
570	609	select CEVT_R4K
..	..	@@ -572,43 +611,6 @@
572	611	select SYS_HAS_CPU_VR41XX
573	612	select SYS_SUPPORTS_MIPS16
574	613	select GPIOLIB
575		-
576		-config NXP_STB220
577		- bool "NXP STB220 board"
578		- select SOC_PNX833X
579		- help
580		- Support for NXP Semiconductors STB220 Development Board.
581		-
582		-config NXP_STB225
583		- bool "NXP 225 board"
584		- select SOC_PNX833X
585		- select SOC_PNX8335
586		- help
587		- Support for NXP Semiconductors STB225 Development Board.
588		-
589		-config PMC_MSP
590		- bool "PMC-Sierra MSP chipsets"
591		- select CEVT_R4K
592		- select CSRC_R4K
593		- select DMA_NONCOHERENT
594		- select SWAP_IO_SPACE
595		- select NO_EXCEPT_FILL
596		- select BOOT_RAW
597		- select SYS_HAS_CPU_MIPS32_R1
598		- select SYS_HAS_CPU_MIPS32_R2
599		- select SYS_SUPPORTS_32BIT_KERNEL
600		- select SYS_SUPPORTS_BIG_ENDIAN
601		- select SYS_SUPPORTS_MIPS16
602		- select IRQ_MIPS_CPU
603		- select SERIAL_8250
604		- select SERIAL_8250_CONSOLE
605		- select USB_EHCI_BIG_ENDIAN_MMIO
606		- select USB_EHCI_BIG_ENDIAN_DESC
607		- help
608		- This adds support for the PMC-Sierra family of Multi-Service
609		- Processor System-On-A-Chips. These parts include a number
610		- of integrated peripherals, interfaces and DSPs in addition to
611		- a variety of MIPS cores.
612	614
613	615	config RALINK
614	616	bool "Ralink based machines"
..	..	@@ -623,6 +625,7 @@
623	625	select SYS_SUPPORTS_32BIT_KERNEL
624	626	select SYS_SUPPORTS_LITTLE_ENDIAN
625	627	select SYS_SUPPORTS_MIPS16
	628	+ select SYS_SUPPORTS_ZBOOT
626	629	select SYS_HAS_EARLY_PRINTK
627	630	select CLKDEV_LOOKUP
628	631	select ARCH_HAS_RESET_CONTROLLER
..	..	@@ -630,6 +633,8 @@
630	633
631	634	config SGI_IP22
632	635	bool "SGI IP22 (Indy/Indigo2)"
	636	+ select ARC_MEMORY
	637	+ select ARC_PROMLIB
633	638	select FW_ARC
634	639	select FW_ARC32
635	640	select ARCH_MIGHT_HAVE_PC_SERIO
..	..	@@ -638,7 +643,7 @@
638	643	select CSRC_R4K
639	644	select DEFAULT_SGI_PARTITION
640	645	select DMA_NONCOHERENT
641		- select HW_HAS_EISA
	646	+ select HAVE_EISA
642	647	select I8253
643	648	select I8259
644	649	select IP22_CPU_SCACHE
..	..	@@ -653,17 +658,13 @@
653	658	select SWAP_IO_SPACE
654	659	select SYS_HAS_CPU_R4X00
655	660	select SYS_HAS_CPU_R5000
656		- #
657		- # Disable EARLY_PRINTK for now since it leads to overwritten prom
658		- # memory during early boot on some machines.
659		- #
660		- # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
661		- # for a more details discussion
662		- #
663		- # select SYS_HAS_EARLY_PRINTK
	661	+ select SYS_HAS_EARLY_PRINTK
664	662	select SYS_SUPPORTS_32BIT_KERNEL
665	663	select SYS_SUPPORTS_64BIT_KERNEL
666	664	select SYS_SUPPORTS_BIG_ENDIAN
	665	+ select WAR_R4600_V1_INDEX_ICACHEOP
	666	+ select WAR_R4600_V1_HIT_CACHEOP
	667	+ select WAR_R4600_V2_HIT_CACHEOP
667	668	select MIPS_L1_CACHE_SHIFT_7
668	669	help
669	670	This are the SGI Indy, Challenge S and Indigo2, as well as certain
..	..	@@ -673,19 +674,27 @@
673	674	config SGI_IP27
674	675	bool "SGI IP27 (Origin200/2000)"
675	676	select ARCH_HAS_PHYS_TO_DMA
	677	+ select ARCH_SPARSEMEM_ENABLE
676	678	select FW_ARC
677	679	select FW_ARC64
	680	+ select ARC_CMDLINE_ONLY
678	681	select BOOT_ELF64
679	682	select DEFAULT_SGI_PARTITION
680	683	select SYS_HAS_EARLY_PRINTK
681		- select HW_HAS_PCI
	684	+ select HAVE_PCI
	685	+ select IRQ_MIPS_CPU
	686	+ select IRQ_DOMAIN_HIERARCHY
682	687	select NR_CPUS_DEFAULT_64
	688	+ select PCI_DRIVERS_GENERIC
	689	+ select PCI_XTALK_BRIDGE
683	690	select SYS_HAS_CPU_R10000
684	691	select SYS_SUPPORTS_64BIT_KERNEL
685	692	select SYS_SUPPORTS_BIG_ENDIAN
686	693	select SYS_SUPPORTS_NUMA
687	694	select SYS_SUPPORTS_SMP
	695	+ select WAR_R10000_LLSC
688	696	select MIPS_L1_CACHE_SHIFT_7
	697	+ select NUMA
689	698	help
690	699	This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
691	700	workstations. To compile a Linux kernel that runs on these, say Y
..	..	@@ -693,6 +702,8 @@
693	702
694	703	config SGI_IP28
695	704	bool "SGI IP28 (Indigo2 R10k)"
	705	+ select ARC_MEMORY
	706	+ select ARC_PROMLIB
696	707	select FW_ARC
697	708	select FW_ARC64
698	709	select ARCH_MIGHT_HAVE_PC_SERIO
..	..	@@ -703,7 +714,7 @@
703	714	select DMA_NONCOHERENT
704	715	select GENERIC_ISA_DMA_SUPPORT_BROKEN
705	716	select IRQ_MIPS_CPU
706		- select HW_HAS_EISA
	717	+ select HAVE_EISA
707	718	select I8253
708	719	select I8259
709	720	select SGI_HAS_I8042
..	..	@@ -714,23 +725,47 @@
714	725	select SGI_HAS_ZILOG
715	726	select SWAP_IO_SPACE
716	727	select SYS_HAS_CPU_R10000
717		- #
718		- # Disable EARLY_PRINTK for now since it leads to overwritten prom
719		- # memory during early boot on some machines.
720		- #
721		- # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
722		- # for a more details discussion
723		- #
724		- # select SYS_HAS_EARLY_PRINTK
	728	+ select SYS_HAS_EARLY_PRINTK
725	729	select SYS_SUPPORTS_64BIT_KERNEL
726	730	select SYS_SUPPORTS_BIG_ENDIAN
	731	+ select WAR_R10000_LLSC
727	732	select MIPS_L1_CACHE_SHIFT_7
728		- help
729		- This is the SGI Indigo2 with R10000 processor. To compile a Linux
730		- kernel that runs on these, say Y here.
	733	+ help
	734	+ This is the SGI Indigo2 with R10000 processor. To compile a Linux
	735	+ kernel that runs on these, say Y here.
	736	+
	737	+config SGI_IP30
	738	+ bool "SGI IP30 (Octane/Octane2)"
	739	+ select ARCH_HAS_PHYS_TO_DMA
	740	+ select FW_ARC
	741	+ select FW_ARC64
	742	+ select BOOT_ELF64
	743	+ select CEVT_R4K
	744	+ select CSRC_R4K
	745	+ select SYNC_R4K if SMP
	746	+ select ZONE_DMA32
	747	+ select HAVE_PCI
	748	+ select IRQ_MIPS_CPU
	749	+ select IRQ_DOMAIN_HIERARCHY
	750	+ select NR_CPUS_DEFAULT_2
	751	+ select PCI_DRIVERS_GENERIC
	752	+ select PCI_XTALK_BRIDGE
	753	+ select SYS_HAS_EARLY_PRINTK
	754	+ select SYS_HAS_CPU_R10000
	755	+ select SYS_SUPPORTS_64BIT_KERNEL
	756	+ select SYS_SUPPORTS_BIG_ENDIAN
	757	+ select SYS_SUPPORTS_SMP
	758	+ select WAR_R10000_LLSC
	759	+ select MIPS_L1_CACHE_SHIFT_7
	760	+ select ARC_MEMORY
	761	+ help
	762	+ These are the SGI Octane and Octane2 graphics workstations. To
	763	+ compile a Linux kernel that runs on these, say Y here.
731	764
732	765	config SGI_IP32
733	766	bool "SGI IP32 (O2)"
	767	+ select ARC_MEMORY
	768	+ select ARC_PROMLIB
734	769	select ARCH_HAS_PHYS_TO_DMA
735	770	select FW_ARC
736	771	select FW_ARC32
..	..	@@ -738,7 +773,7 @@
738	773	select CEVT_R4K
739	774	select CSRC_R4K
740	775	select DMA_NONCOHERENT
741		- select HW_HAS_PCI
	776	+ select HAVE_PCI
742	777	select IRQ_MIPS_CPU
743	778	select R5000_CPU_SCACHE
744	779	select RM7000_CPU_SCACHE
..	..	@@ -748,6 +783,7 @@
748	783	select SYS_HAS_CPU_NEVADA
749	784	select SYS_SUPPORTS_64BIT_KERNEL
750	785	select SYS_SUPPORTS_BIG_ENDIAN
	786	+ select WAR_ICACHE_REFILLS
751	787	help
752	788	If you want this kernel to run on SGI O2 workstation, say Y here.
753	789
..	..	@@ -838,6 +874,8 @@
838	874
839	875	config SNI_RM
840	876	bool "SNI RM200/300/400"
	877	+ select ARC_MEMORY
	878	+ select ARC_PROMLIB
841	879	select FW_ARC if CPU_LITTLE_ENDIAN
842	880	select FW_ARC32 if CPU_LITTLE_ENDIAN
843	881	select FW_SNIPROM if CPU_BIG_ENDIAN
..	..	@@ -850,9 +888,9 @@
850	888	select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
851	889	select DMA_NONCOHERENT
852	890	select GENERIC_ISA_DMA
	891	+ select HAVE_EISA
853	892	select HAVE_PCSPKR_PLATFORM
854		- select HW_HAS_EISA
855		- select HW_HAS_PCI
	893	+ select HAVE_PCI
856	894	select IRQ_MIPS_CPU
857	895	select I8253
858	896	select I8259
..	..	@@ -869,6 +907,7 @@
869	907	select SYS_SUPPORTS_BIG_ENDIAN
870	908	select SYS_SUPPORTS_HIGHMEM
871	909	select SYS_SUPPORTS_LITTLE_ENDIAN
	910	+ select WAR_R4600_V2_HIT_CACHEOP
872	911	help
873	912	The SNI RM200/300/400 are MIPS-based machines manufactured by
874	913	Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
..	..	@@ -880,13 +919,14 @@
880	919
881	920	config MACH_TX49XX
882	921	bool "Toshiba TX49 series based machines"
	922	+ select WAR_TX49XX_ICACHE_INDEX_INV
883	923
884	924	config MIKROTIK_RB532
885	925	bool "Mikrotik RB532 boards"
886	926	select CEVT_R4K
887	927	select CSRC_R4K
888	928	select DMA_NONCOHERENT
889		- select HW_HAS_PCI
	929	+ select HAVE_PCI
890	930	select IRQ_MIPS_CPU
891	931	select SYS_HAS_CPU_MIPS32_R1
892	932	select SYS_SUPPORTS_32BIT_KERNEL
..	..	@@ -903,7 +943,7 @@
903	943	bool "Cavium Networks Octeon SoC based boards"
904	944	select CEVT_R4K
905	945	select ARCH_HAS_PHYS_TO_DMA
906		- select HAS_RAPIDIO
	946	+ select HAVE_RAPIDIO
907	947	select PHYS_ADDR_T_64BIT
908	948	select SYS_SUPPORTS_64BIT_KERNEL
909	949	select SYS_SUPPORTS_BIG_ENDIAN
..	..	@@ -913,11 +953,13 @@
913	953	select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
914	954	select SYS_HAS_EARLY_PRINTK
915	955	select SYS_HAS_CPU_CAVIUM_OCTEON
916		- select HW_HAS_PCI
	956	+ select HAVE_PCI
	957	+ select HAVE_PLAT_DELAY
	958	+ select HAVE_PLAT_FW_INIT_CMDLINE
	959	+ select HAVE_PLAT_MEMCPY
917	960	select ZONE_DMA32
918	961	select HOLES_IN_ZONE
919	962	select GPIOLIB
920		- select LIBFDT
921	963	select USE_OF
922	964	select ARCH_SPARSEMEM_ENABLE
923	965	select SYS_SUPPORTS_SMP
..	..	@@ -946,7 +988,7 @@
946	988	select NLM_COMMON
947	989	select SYS_HAS_CPU_XLR
948	990	select SYS_SUPPORTS_SMP
949		- select HW_HAS_PCI
	991	+ select HAVE_PCI
950	992	select SWAP_IO_SPACE
951	993	select SYS_SUPPORTS_32BIT_KERNEL
952	994	select SYS_SUPPORTS_64BIT_KERNEL
..	..	@@ -972,7 +1014,7 @@
972	1014	select NLM_COMMON
973	1015	select SYS_HAS_CPU_XLP
974	1016	select SYS_SUPPORTS_SMP
975		- select HW_HAS_PCI
	1017	+ select HAVE_PCI
976	1018	select SYS_SUPPORTS_32BIT_KERNEL
977	1019	select SYS_SUPPORTS_64BIT_KERNEL
978	1020	select PHYS_ADDR_T_64BIT
..	..	@@ -994,24 +1036,6 @@
994	1036	This board is based on Netlogic XLP Processor.
995	1037	Say Y here if you have a XLP based board.
996	1038
997		-config MIPS_PARAVIRT
998		- bool "Para-Virtualized guest system"
999		- select CEVT_R4K
1000		- select CSRC_R4K
1001		- select SYS_SUPPORTS_64BIT_KERNEL
1002		- select SYS_SUPPORTS_32BIT_KERNEL
1003		- select SYS_SUPPORTS_BIG_ENDIAN
1004		- select SYS_SUPPORTS_SMP
1005		- select NR_CPUS_DEFAULT_4
1006		- select SYS_HAS_EARLY_PRINTK
1007		- select SYS_HAS_CPU_MIPS32_R2
1008		- select SYS_HAS_CPU_MIPS64_R2
1009		- select SYS_HAS_CPU_CAVIUM_OCTEON
1010		- select HW_HAS_PCI
1011		- select SWAP_IO_SPACE
1012		- help
1013		- This option supports guest running under ????
1014		-
1015	1039	endchoice
1016	1040
1017	1041	source "arch/mips/alchemy/Kconfig"
..	..	@@ -1021,32 +1045,23 @@
1021	1045	source "arch/mips/bcm63xx/Kconfig"
1022	1046	source "arch/mips/bmips/Kconfig"
1023	1047	source "arch/mips/generic/Kconfig"
	1048	+source "arch/mips/ingenic/Kconfig"
1024	1049	source "arch/mips/jazz/Kconfig"
1025		-source "arch/mips/jz4740/Kconfig"
1026	1050	source "arch/mips/lantiq/Kconfig"
1027		-source "arch/mips/lasat/Kconfig"
1028	1051	source "arch/mips/pic32/Kconfig"
1029	1052	source "arch/mips/pistachio/Kconfig"
1030		-source "arch/mips/pmcs-msp71xx/Kconfig"
1031	1053	source "arch/mips/ralink/Kconfig"
1032	1054	source "arch/mips/sgi-ip27/Kconfig"
1033	1055	source "arch/mips/sibyte/Kconfig"
1034	1056	source "arch/mips/txx9/Kconfig"
1035	1057	source "arch/mips/vr41xx/Kconfig"
1036	1058	source "arch/mips/cavium-octeon/Kconfig"
	1059	+source "arch/mips/loongson2ef/Kconfig"
1037	1060	source "arch/mips/loongson32/Kconfig"
1038	1061	source "arch/mips/loongson64/Kconfig"
1039	1062	source "arch/mips/netlogic/Kconfig"
1040		-source "arch/mips/paravirt/Kconfig"
1041	1063
1042	1064	endmenu
1043		-
1044		-config RWSEM_GENERIC_SPINLOCK
1045		- bool
1046		- default y
1047		-
1048		-config RWSEM_XCHGADD_ALGORITHM
1049		- bool
1050	1065
1051	1066	config GENERIC_HWEIGHT
1052	1067	bool
..	..	@@ -1097,6 +1112,7 @@
1097	1112	bool
1098	1113
1099	1114	config CSRC_R4K
	1115	+ select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1100	1116	bool
1101	1117
1102	1118	config CSRC_SB1250
..	..	@@ -1116,21 +1132,30 @@
1116	1132	bool
1117	1133
1118	1134	config DMA_MAYBE_COHERENT
	1135	+ select ARCH_HAS_DMA_COHERENCE_H
1119	1136	select DMA_NONCOHERENT
1120	1137	bool
1121	1138
1122	1139	config DMA_PERDEV_COHERENT
1123	1140	bool
1124		- select DMA_MAYBE_COHERENT
	1141	+ select ARCH_HAS_SETUP_DMA_OPS
	1142	+ select DMA_NONCOHERENT
1125	1143
1126	1144	config DMA_NONCOHERENT
1127	1145	bool
	1146	+ #
	1147	+ # MIPS allows mixing "slightly different" Cacheability and Coherency
	1148	+ # Attribute bits. It is believed that the uncached access through
	1149	+ # KSEG1 and the implementation specific "uncached accelerated" used
	1150	+ # by pgprot_writcombine can be mixed, and the latter sometimes provides
	1151	+ # significant advantages.
	1152	+ #
	1153	+ select ARCH_HAS_DMA_WRITE_COMBINE
	1154	+ select ARCH_HAS_DMA_PREP_COHERENT
1128	1155	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
1129		- select ARCH_HAS_SYNC_DMA_FOR_CPU
1130		- select NEED_DMA_MAP_STATE
	1156	+ select ARCH_HAS_DMA_SET_UNCACHED
1131	1157	select DMA_NONCOHERENT_MMAP
1132		- select DMA_NONCOHERENT_CACHE_SYNC
1133		- select DMA_NONCOHERENT_OPS
	1158	+ select NEED_DMA_MAP_STATE
1134	1159
1135	1160	config SYS_HAS_EARLY_PRINTK
1136	1161	bool
..	..	@@ -1144,20 +1169,14 @@
1144	1169	config MIPS_MSC
1145	1170	bool
1146	1171
1147		-config MIPS_NILE4
1148		- bool
1149		-
1150	1172	config SYNC_R4K
1151	1173	bool
1152		-
1153		-config MIPS_MACHINE
1154		- def_bool n
1155	1174
1156	1175	config NO_IOPORT_MAP
1157	1176	def_bool n
1158	1177
1159	1178	config GENERIC_CSUM
1160		- bool
	1179	+ def_bool CPU_NO_LOAD_STORE_LR
1161	1180
1162	1181	config GENERIC_ISA_DMA
1163	1182	bool
..	..	@@ -1168,6 +1187,15 @@
1168	1187	bool
1169	1188	select GENERIC_ISA_DMA
1170	1189
	1190	+config HAVE_PLAT_DELAY
	1191	+ bool
	1192	+
	1193	+config HAVE_PLAT_FW_INIT_CMDLINE
	1194	+ bool
	1195	+
	1196	+config HAVE_PLAT_MEMCPY
	1197	+ bool
	1198	+
1171	1199	config ISA_DMA_API
1172	1200	bool
1173	1201
..	..	@@ -1177,9 +1205,9 @@
1177	1205	config SYS_SUPPORTS_RELOCATABLE
1178	1206	bool
1179	1207	help
1180		- Selected if the platform supports relocating the kernel.
1181		- The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1182		- to allow access to command line and entropy sources.
	1208	+ Selected if the platform supports relocating the kernel.
	1209	+ The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
	1210	+ to allow access to command line and entropy sources.
1183	1211
1184	1212	config MIPS_CBPF_JIT
1185	1213	def_bool y
..	..	@@ -1228,7 +1256,7 @@
1228	1256
1229	1257	config SYS_SUPPORTS_HUGETLBFS
1230	1258	bool
1231		- depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
	1259	+ depends on CPU_SUPPORTS_HUGEPAGES
1232	1260	default y
1233	1261
1234	1262	config MIPS_HUGE_TLB_SUPPORT
..	..	@@ -1252,37 +1280,11 @@
1252	1280	config PCI_GT64XXX_PCI0
1253	1281	bool
1254	1282
	1283	+config PCI_XTALK_BRIDGE
	1284	+ bool
	1285	+
1255	1286	config NO_EXCEPT_FILL
1256	1287	bool
1257		-
1258		-config SOC_EMMA2RH
1259		- bool
1260		- select CEVT_R4K
1261		- select CSRC_R4K
1262		- select DMA_NONCOHERENT
1263		- select IRQ_MIPS_CPU
1264		- select SWAP_IO_SPACE
1265		- select SYS_HAS_CPU_R5500
1266		- select SYS_SUPPORTS_32BIT_KERNEL
1267		- select SYS_SUPPORTS_64BIT_KERNEL
1268		- select SYS_SUPPORTS_BIG_ENDIAN
1269		-
1270		-config SOC_PNX833X
1271		- bool
1272		- select CEVT_R4K
1273		- select CSRC_R4K
1274		- select IRQ_MIPS_CPU
1275		- select DMA_NONCOHERENT
1276		- select SYS_HAS_CPU_MIPS32_R2
1277		- select SYS_SUPPORTS_32BIT_KERNEL
1278		- select SYS_SUPPORTS_LITTLE_ENDIAN
1279		- select SYS_SUPPORTS_BIG_ENDIAN
1280		- select SYS_SUPPORTS_MIPS16
1281		- select CPU_MIPSR2_IRQ_VI
1282		-
1283		-config SOC_PNX8335
1284		- bool
1285		- select SOC_PNX833X
1286	1288
1287	1289	config MIPS_SPRAM
1288	1290	bool
..	..	@@ -1340,7 +1342,7 @@
1340	1342	default "4" if MIPS_L1_CACHE_SHIFT_4
1341	1343	default "5"
1342	1344
1343		-config HAVE_STD_PC_SERIAL_PORT
	1345	+config ARC_CMDLINE_ONLY
1344	1346	bool
1345	1347
1346	1348	config ARC_CONSOLE
..	..	@@ -1349,13 +1351,9 @@
1349	1351
1350	1352	config ARC_MEMORY
1351	1353	bool
1352		- depends on MACH_JAZZ \|\| SNI_RM \|\| SGI_IP32
1353		- default y
1354	1354
1355	1355	config ARC_PROMLIB
1356	1356	bool
1357		- depends on MACH_JAZZ \|\| SNI_RM \|\| SGI_IP22 \|\| SGI_IP28 \|\| SGI_IP32
1358		- default y
1359	1357
1360	1358	config FW_ARC64
1361	1359	bool
..	..	@@ -1369,46 +1367,81 @@
1369	1367	prompt "CPU type"
1370	1368	default CPU_R4X00
1371	1369
1372		-config CPU_LOONGSON3
1373		- bool "Loongson 3 CPU"
1374		- depends on SYS_HAS_CPU_LOONGSON3
	1370	+config CPU_LOONGSON64
	1371	+ bool "Loongson 64-bit CPU"
	1372	+ depends on SYS_HAS_CPU_LOONGSON64
1375	1373	select ARCH_HAS_PHYS_TO_DMA
	1374	+ select CPU_MIPSR2
	1375	+ select CPU_HAS_PREFETCH
1376	1376	select CPU_SUPPORTS_64BIT_KERNEL
1377	1377	select CPU_SUPPORTS_HIGHMEM
1378	1378	select CPU_SUPPORTS_HUGEPAGES
	1379	+ select CPU_SUPPORTS_MSA
	1380	+ select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
	1381	+ select CPU_MIPSR2_IRQ_VI
1379	1382	select WEAK_ORDERING
1380	1383	select WEAK_REORDERING_BEYOND_LLSC
	1384	+ select MIPS_ASID_BITS_VARIABLE
1381	1385	select MIPS_PGD_C0_CONTEXT
1382	1386	select MIPS_L1_CACHE_SHIFT_6
1383	1387	select MIPS_FP_SUPPORT
1384	1388	select GPIOLIB
1385	1389	select SWIOTLB
	1390	+ select HAVE_KVM
1386	1391	help
1387		- The Loongson 3 processor implements the MIPS64R2 instruction
1388		- set with many extensions.
	1392	+ The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
	1393	+ cores implements the MIPS64R2 instruction set with many extensions,
	1394	+ including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
	1395	+ 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
	1396	+ Loongson-2E/2F is not covered here and will be removed in future.
1389	1397
1390	1398	config LOONGSON3_ENHANCEMENT
1391		- bool "New Loongson 3 CPU Enhancements"
	1399	+ bool "New Loongson-3 CPU Enhancements"
1392	1400	default n
1393		- select CPU_MIPSR2
1394		- select CPU_HAS_PREFETCH
1395		- depends on CPU_LOONGSON3
	1401	+ depends on CPU_LOONGSON64
1396	1402	help
1397		- New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
	1403	+ New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1398	1404	R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1399		- FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
	1405	+ FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1400	1406	Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1401	1407	Fast TLB refill support, etc.
1402	1408
1403	1409	This option enable those enhancements which are not probed at run
1404	1410	time. If you want a generic kernel to run on all Loongson 3 machines,
1405	1411	please say 'N' here. If you want a high-performance kernel to run on
1406		- new Loongson 3 machines only, please say 'Y' here.
	1412	+ new Loongson-3 machines only, please say 'Y' here.
	1413	+
	1414	+config CPU_LOONGSON3_WORKAROUNDS
	1415	+ bool "Old Loongson-3 LLSC Workarounds"
	1416	+ default y if SMP
	1417	+ depends on CPU_LOONGSON64
	1418	+ help
	1419	+ Loongson-3 processors have the llsc issues which require workarounds.
	1420	+ Without workarounds the system may hang unexpectedly.
	1421	+
	1422	+ Newer Loongson-3 will fix these issues and no workarounds are needed.
	1423	+ The workarounds have no significant side effect on them but may
	1424	+ decrease the performance of the system so this option should be
	1425	+ disabled unless the kernel is intended to be run on old systems.
	1426	+
	1427	+ If unsure, please say Y.
	1428	+
	1429	+config CPU_LOONGSON3_CPUCFG_EMULATION
	1430	+ bool "Emulate the CPUCFG instruction on older Loongson cores"
	1431	+ default y
	1432	+ depends on CPU_LOONGSON64
	1433	+ help
	1434	+ Loongson-3A R4 and newer have the CPUCFG instruction available for
	1435	+ userland to query CPU capabilities, much like CPUID on x86. This
	1436	+ option provides emulation of the instruction on older Loongson
	1437	+ cores, back to Loongson-3A1000.
	1438	+
	1439	+ If unsure, please say Y.
1407	1440
1408	1441	config CPU_LOONGSON2E
1409	1442	bool "Loongson 2E"
1410	1443	depends on SYS_HAS_CPU_LOONGSON2E
1411		- select CPU_LOONGSON2
	1444	+ select CPU_LOONGSON2EF
1412	1445	help
1413	1446	The Loongson 2E processor implements the MIPS III instruction set
1414	1447	with many extensions.
..	..	@@ -1419,7 +1452,7 @@
1419	1452	config CPU_LOONGSON2F
1420	1453	bool "Loongson 2F"
1421	1454	depends on SYS_HAS_CPU_LOONGSON2F
1422		- select CPU_LOONGSON2
	1455	+ select CPU_LOONGSON2EF
1423	1456	select GPIOLIB
1424	1457	help
1425	1458	The Loongson 2F processor implements the MIPS III instruction set
..	..	@@ -1432,7 +1465,7 @@
1432	1465	config CPU_LOONGSON1B
1433	1466	bool "Loongson 1B"
1434	1467	depends on SYS_HAS_CPU_LOONGSON1B
1435		- select CPU_LOONGSON1
	1468	+ select CPU_LOONGSON32
1436	1469	select LEDS_GPIO_REGISTER
1437	1470	help
1438	1471	The Loongson 1B is a 32-bit SoC, which implements the MIPS32
..	..	@@ -1442,7 +1475,7 @@
1442	1475	config CPU_LOONGSON1C
1443	1476	bool "Loongson 1C"
1444	1477	depends on SYS_HAS_CPU_LOONGSON1C
1445		- select CPU_LOONGSON1
	1478	+ select CPU_LOONGSON32
1446	1479	select LEDS_GPIO_REGISTER
1447	1480	help
1448	1481	The Loongson 1C is a 32-bit SoC, which implements the MIPS32
..	..	@@ -1481,14 +1514,29 @@
1481	1514	specific type of processor in your system, choose those that one
1482	1515	otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1483	1516
1484		-config CPU_MIPS32_R6
1485		- bool "MIPS32 Release 6"
1486		- depends on SYS_HAS_CPU_MIPS32_R6
	1517	+config CPU_MIPS32_R5
	1518	+ bool "MIPS32 Release 5"
	1519	+ depends on SYS_HAS_CPU_MIPS32_R5
1487	1520	select CPU_HAS_PREFETCH
1488	1521	select CPU_SUPPORTS_32BIT_KERNEL
1489	1522	select CPU_SUPPORTS_HIGHMEM
1490	1523	select CPU_SUPPORTS_MSA
1491		- select GENERIC_CSUM
	1524	+ select HAVE_KVM
	1525	+ select MIPS_O32_FP64_SUPPORT
	1526	+ help
	1527	+ Choose this option to build a kernel for release 5 or later of the
	1528	+ MIPS32 architecture. New MIPS processors, starting with the Warrior
	1529	+ family, are based on a MIPS32r5 processor. If you own an older
	1530	+ processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
	1531	+
	1532	+config CPU_MIPS32_R6
	1533	+ bool "MIPS32 Release 6"
	1534	+ depends on SYS_HAS_CPU_MIPS32_R6
	1535	+ select CPU_HAS_PREFETCH
	1536	+ select CPU_NO_LOAD_STORE_LR
	1537	+ select CPU_SUPPORTS_32BIT_KERNEL
	1538	+ select CPU_SUPPORTS_HIGHMEM
	1539	+ select CPU_SUPPORTS_MSA
1492	1540	select HAVE_KVM
1493	1541	select MIPS_O32_FP64_SUPPORT
1494	1542	help
..	..	@@ -1533,15 +1581,33 @@
1533	1581	specific type of processor in your system, choose those that one
1534	1582	otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1535	1583
1536		-config CPU_MIPS64_R6
1537		- bool "MIPS64 Release 6"
1538		- depends on SYS_HAS_CPU_MIPS64_R6
	1584	+config CPU_MIPS64_R5
	1585	+ bool "MIPS64 Release 5"
	1586	+ depends on SYS_HAS_CPU_MIPS64_R5
1539	1587	select CPU_HAS_PREFETCH
1540	1588	select CPU_SUPPORTS_32BIT_KERNEL
1541	1589	select CPU_SUPPORTS_64BIT_KERNEL
1542	1590	select CPU_SUPPORTS_HIGHMEM
	1591	+ select CPU_SUPPORTS_HUGEPAGES
1543	1592	select CPU_SUPPORTS_MSA
1544		- select GENERIC_CSUM
	1593	+ select MIPS_O32_FP64_SUPPORT if 32BIT \|\| MIPS32_O32
	1594	+ select HAVE_KVM
	1595	+ help
	1596	+ Choose this option to build a kernel for release 5 or later of the
	1597	+ MIPS64 architecture. This is a intermediate MIPS architecture
	1598	+ release partly implementing release 6 features. Though there is no
	1599	+ any hardware known to be based on this release.
	1600	+
	1601	+config CPU_MIPS64_R6
	1602	+ bool "MIPS64 Release 6"
	1603	+ depends on SYS_HAS_CPU_MIPS64_R6
	1604	+ select CPU_HAS_PREFETCH
	1605	+ select CPU_NO_LOAD_STORE_LR
	1606	+ select CPU_SUPPORTS_32BIT_KERNEL
	1607	+ select CPU_SUPPORTS_64BIT_KERNEL
	1608	+ select CPU_SUPPORTS_HIGHMEM
	1609	+ select CPU_SUPPORTS_HUGEPAGES
	1610	+ select CPU_SUPPORTS_MSA
1545	1611	select MIPS_O32_FP64_SUPPORT if 32BIT \|\| MIPS32_O32
1546	1612	select HAVE_KVM
1547	1613	help
..	..	@@ -1550,10 +1616,32 @@
1550	1616	family, are based on a MIPS64r6 processor. If you own an older
1551	1617	processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1552	1618
	1619	+config CPU_P5600
	1620	+ bool "MIPS Warrior P5600"
	1621	+ depends on SYS_HAS_CPU_P5600
	1622	+ select CPU_HAS_PREFETCH
	1623	+ select CPU_SUPPORTS_32BIT_KERNEL
	1624	+ select CPU_SUPPORTS_HIGHMEM
	1625	+ select CPU_SUPPORTS_MSA
	1626	+ select CPU_SUPPORTS_CPUFREQ
	1627	+ select CPU_MIPSR2_IRQ_VI
	1628	+ select CPU_MIPSR2_IRQ_EI
	1629	+ select HAVE_KVM
	1630	+ select MIPS_O32_FP64_SUPPORT
	1631	+ help
	1632	+ Choose this option to build a kernel for MIPS Warrior P5600 CPU.
	1633	+ It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
	1634	+ MMU with two-levels TLB, UCA, MSA, MDU core level features and system
	1635	+ level features like up to six P5600 calculation cores, CM2 with L2
	1636	+ cache, IOCU/IOMMU (though might be unused depending on the system-
	1637	+ specific IP core configuration), GIC, CPC, virtualisation module,
	1638	+ eJTAG and PDtrace.
	1639	+
1553	1640	config CPU_R3000
1554	1641	bool "R3000"
1555	1642	depends on SYS_HAS_CPU_R3000
1556	1643	select CPU_HAS_WB
	1644	+ select CPU_R3K_TLB
1557	1645	select CPU_SUPPORTS_32BIT_KERNEL
1558	1646	select CPU_SUPPORTS_HIGHMEM
1559	1647	help
..	..	@@ -1568,6 +1656,7 @@
1568	1656	bool "R39XX"
1569	1657	depends on SYS_HAS_CPU_TX39XX
1570	1658	select CPU_SUPPORTS_32BIT_KERNEL
	1659	+ select CPU_R3K_TLB
1571	1660
1572	1661	config CPU_VR41XX
1573	1662	bool "R41xx"
..	..	@@ -1579,14 +1668,6 @@
1579	1668	Only choose this option if you have one of these processors as a
1580	1669	kernel built with this option will not run on any other type of
1581	1670	processor or vice versa.
1582		-
1583		-config CPU_R4300
1584		- bool "R4300"
1585		- depends on SYS_HAS_CPU_R4300
1586		- select CPU_SUPPORTS_32BIT_KERNEL
1587		- select CPU_SUPPORTS_64BIT_KERNEL
1588		- help
1589		- MIPS Technologies R4300-series processors.
1590	1671
1591	1672	config CPU_R4X00
1592	1673	bool "R4x00"
..	..	@@ -1615,13 +1696,6 @@
1615	1696	help
1616	1697	MIPS Technologies R5000-series processors other than the Nevada.
1617	1698
1618		-config CPU_R5432
1619		- bool "R5432"
1620		- depends on SYS_HAS_CPU_R5432
1621		- select CPU_SUPPORTS_32BIT_KERNEL
1622		- select CPU_SUPPORTS_64BIT_KERNEL
1623		- select CPU_SUPPORTS_HUGEPAGES
1624		-
1625	1699	config CPU_R5500
1626	1700	bool "R5500"
1627	1701	depends on SYS_HAS_CPU_R5500
..	..	@@ -1640,15 +1714,6 @@
1640	1714	select CPU_SUPPORTS_HUGEPAGES
1641	1715	help
1642	1716	QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1643		-
1644		-config CPU_R8000
1645		- bool "R8000"
1646		- depends on SYS_HAS_CPU_R8000
1647		- select CPU_HAS_PREFETCH
1648		- select CPU_SUPPORTS_64BIT_KERNEL
1649		- help
1650		- MIPS Technologies R8000 processors. Note these processors are
1651		- uncommon and the support for them is incomplete.
1652	1717
1653	1718	config CPU_R10000
1654	1719	bool "R10000"
..	..	@@ -1748,7 +1813,8 @@
1748	1813	config CPU_MIPS32_3_5_FEATURES
1749	1814	bool "MIPS32 Release 3.5 Features"
1750	1815	depends on SYS_HAS_CPU_MIPS32_R3_5
1751		- depends on CPU_MIPS32_R2 \|\| CPU_MIPS32_R6
	1816	+ depends on CPU_MIPS32_R2 \|\| CPU_MIPS32_R5 \|\| CPU_MIPS32_R6 \|\| \
	1817	+ CPU_P5600
1752	1818	help
1753	1819	Choose this option to build a kernel for release 2 or later of the
1754	1820	MIPS32 architecture including features from the 3.5 release such as
..	..	@@ -1768,7 +1834,7 @@
1768	1834	config CPU_MIPS32_R5_FEATURES
1769	1835	bool "MIPS32 Release 5 Features"
1770	1836	depends on SYS_HAS_CPU_MIPS32_R5
1771		- depends on CPU_MIPS32_R2
	1837	+ depends on CPU_MIPS32_R2 \|\| CPU_MIPS32_R5 \|\| CPU_P5600
1772	1838	help
1773	1839	Choose this option to build a kernel for release 2 or later of the
1774	1840	MIPS32 architecture including features from release 5 such as
..	..	@@ -1827,6 +1893,7 @@
1827	1893	select HAVE_KERNEL_LZMA
1828	1894	select HAVE_KERNEL_LZO
1829	1895	select HAVE_KERNEL_XZ
	1896	+ select HAVE_KERNEL_ZSTD
1830	1897
1831	1898	config SYS_SUPPORTS_ZBOOT_UART16550
1832	1899	bool
..	..	@@ -1836,7 +1903,7 @@
1836	1903	bool
1837	1904	select SYS_SUPPORTS_ZBOOT
1838	1905
1839		-config CPU_LOONGSON2
	1906	+config CPU_LOONGSON2EF
1840	1907	bool
1841	1908	select CPU_SUPPORTS_32BIT_KERNEL
1842	1909	select CPU_SUPPORTS_64BIT_KERNEL
..	..	@@ -1844,10 +1911,10 @@
1844	1911	select CPU_SUPPORTS_HUGEPAGES
1845	1912	select ARCH_HAS_PHYS_TO_DMA
1846	1913
1847		-config CPU_LOONGSON1
	1914	+config CPU_LOONGSON32
1848	1915	bool
1849	1916	select CPU_MIPS32
1850		- select CPU_MIPSR1
	1917	+ select CPU_MIPSR2
1851	1918	select CPU_HAS_PREFETCH
1852	1919	select CPU_SUPPORTS_32BIT_KERNEL
1853	1920	select CPU_SUPPORTS_HIGHMEM
..	..	@@ -1877,7 +1944,7 @@
1877	1944	select SYS_SUPPORTS_HOTPLUG_CPU
1878	1945	select CPU_HAS_RIXI
1879	1946
1880		-config SYS_HAS_CPU_LOONGSON3
	1947	+config SYS_HAS_CPU_LOONGSON64
1881	1948	bool
1882	1949	select CPU_SUPPORTS_CPUFREQ
1883	1950	select CPU_HAS_RIXI
..	..	@@ -1889,7 +1956,6 @@
1889	1956	bool
1890	1957	select CPU_SUPPORTS_CPUFREQ
1891	1958	select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1892		- select CPU_SUPPORTS_UNCACHED_ACCELERATED
1893	1959
1894	1960	config SYS_HAS_CPU_LOONGSON1B
1895	1961	bool
..	..	@@ -1908,9 +1974,11 @@
1908	1974
1909	1975	config SYS_HAS_CPU_MIPS32_R5
1910	1976	bool
	1977	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1911	1978
1912	1979	config SYS_HAS_CPU_MIPS32_R6
1913	1980	bool
	1981	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1914	1982
1915	1983	config SYS_HAS_CPU_MIPS64_R1
1916	1984	bool
..	..	@@ -1918,8 +1986,17 @@
1918	1986	config SYS_HAS_CPU_MIPS64_R2
1919	1987	bool
1920	1988
	1989	+config SYS_HAS_CPU_MIPS64_R5
	1990	+ bool
	1991	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
	1992	+
1921	1993	config SYS_HAS_CPU_MIPS64_R6
1922	1994	bool
	1995	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
	1996	+
	1997	+config SYS_HAS_CPU_P5600
	1998	+ bool
	1999	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1923	2000
1924	2001	config SYS_HAS_CPU_R3000
1925	2002	bool
..	..	@@ -1928,9 +2005,6 @@
1928	2005	bool
1929	2006
1930	2007	config SYS_HAS_CPU_VR41XX
1931		- bool
1932		-
1933		-config SYS_HAS_CPU_R4300
1934	2008	bool
1935	2009
1936	2010	config SYS_HAS_CPU_R4X00
..	..	@@ -1942,20 +2016,15 @@
1942	2016	config SYS_HAS_CPU_R5000
1943	2017	bool
1944	2018
1945		-config SYS_HAS_CPU_R5432
1946		- bool
1947		-
1948	2019	config SYS_HAS_CPU_R5500
1949	2020	bool
1950	2021
1951	2022	config SYS_HAS_CPU_NEVADA
1952	2023	bool
1953	2024
1954		-config SYS_HAS_CPU_R8000
1955		- bool
1956		-
1957	2025	config SYS_HAS_CPU_R10000
1958	2026	bool
	2027	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1959	2028
1960	2029	config SYS_HAS_CPU_RM7000
1961	2030	bool
..	..	@@ -1984,6 +2053,7 @@
1984	2053	config SYS_HAS_CPU_BMIPS5000
1985	2054	bool
1986	2055	select SYS_HAS_CPU_BMIPS
	2056	+ select ARCH_HAS_SYNC_DMA_FOR_CPU
1987	2057
1988	2058	config SYS_HAS_CPU_XLR
1989	2059	bool
..	..	@@ -2011,14 +2081,16 @@
2011	2081	#
2012	2082	config CPU_MIPS32
2013	2083	bool
2014		- default y if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2 \|\| CPU_MIPS32_R6
	2084	+ default y if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2 \|\| CPU_MIPS32_R5 \|\| \
	2085	+ CPU_MIPS32_R6 \|\| CPU_P5600
2015	2086
2016	2087	config CPU_MIPS64
2017	2088	bool
2018		- default y if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS64_R6
	2089	+ default y if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS64_R5 \|\| \
	2090	+ CPU_MIPS64_R6
2019	2091
2020	2092	#
2021		-# These two indicate the revision of the architecture, either Release 1 or Release 2
	2093	+# These indicate the revision of the architecture
2022	2094	#
2023	2095	config CPU_MIPSR1
2024	2096	bool
..	..	@@ -2028,16 +2100,36 @@
2028	2100	bool
2029	2101	default y if CPU_MIPS32_R2 \|\| CPU_MIPS64_R2 \|\| CPU_CAVIUM_OCTEON
2030	2102	select CPU_HAS_RIXI
	2103	+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
	2104	+ select MIPS_SPRAM
	2105	+
	2106	+config CPU_MIPSR5
	2107	+ bool
	2108	+ default y if CPU_MIPS32_R5 \|\| CPU_MIPS64_R5 \|\| CPU_P5600
	2109	+ select CPU_HAS_RIXI
	2110	+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
2031	2111	select MIPS_SPRAM
2032	2112
2033	2113	config CPU_MIPSR6
2034	2114	bool
2035	2115	default y if CPU_MIPS32_R6 \|\| CPU_MIPS64_R6
2036	2116	select CPU_HAS_RIXI
	2117	+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
2037	2118	select HAVE_ARCH_BITREVERSE
2038	2119	select MIPS_ASID_BITS_VARIABLE
2039	2120	select MIPS_CRC_SUPPORT
2040	2121	select MIPS_SPRAM
	2122	+
	2123	+config TARGET_ISA_REV
	2124	+ int
	2125	+ default 1 if CPU_MIPSR1
	2126	+ default 2 if CPU_MIPSR2
	2127	+ default 5 if CPU_MIPSR5
	2128	+ default 6 if CPU_MIPSR6
	2129	+ default 0
	2130	+ help
	2131	+ Reflects the ISA revision being targeted by the kernel build. This
	2132	+ is effectively the Kconfig equivalent of MIPS_ISA_REV.
2041	2133
2042	2134	config EVA
2043	2135	bool
..	..	@@ -2059,8 +2151,7 @@
2059	2151	bool
2060	2152	config CPU_SUPPORTS_HUGEPAGES
2061	2153	bool
2062		-config CPU_SUPPORTS_UNCACHED_ACCELERATED
2063		- bool
	2154	+ depends on !(32BIT && (PHYS_ADDR_T_64BIT \|\| EVA))
2064	2155	config MIPS_PGD_C0_CONTEXT
2065	2156	bool
2066	2157	default y if 64BIT && (CPU_MIPSR2 \|\| CPU_MIPSR6) && !CPU_XLP
..	..	@@ -2069,8 +2160,8 @@
2069	2160	# Set to y for ptrace access to watch registers.
2070	2161	#
2071	2162	config HARDWARE_WATCHPOINTS
2072		- bool
2073		- default y if CPU_MIPSR1 \|\| CPU_MIPSR2 \|\| CPU_MIPSR6
	2163	+ bool
	2164	+ default y if CPU_MIPSR1 \|\| CPU_MIPSR2 \|\| CPU_MIPSR6
2074	2165
2075	2166	menu "Kernel type"
2076	2167
..	..	@@ -2099,6 +2190,7 @@
2099	2190
2100	2191	config KVM_GUEST
2101	2192	bool "KVM Guest Kernel"
	2193	+ depends on CPU_MIPS32_R2
2102	2194	depends on BROKEN_ON_SMP
2103	2195	help
2104	2196	Select this option if building a guest kernel for KVM (Trap & Emulate)
..	..	@@ -2132,22 +2224,22 @@
2132	2224
2133	2225	config PAGE_SIZE_4KB
2134	2226	bool "4kB"
2135		- depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
	2227	+ depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
2136	2228	help
2137		- This option select the standard 4kB Linux page size. On some
2138		- R3000-family processors this is the only available page size. Using
2139		- 4kB page size will minimize memory consumption and is therefore
2140		- recommended for low memory systems.
	2229	+ This option select the standard 4kB Linux page size. On some
	2230	+ R3000-family processors this is the only available page size. Using
	2231	+ 4kB page size will minimize memory consumption and is therefore
	2232	+ recommended for low memory systems.
2141	2233
2142	2234	config PAGE_SIZE_8KB
2143	2235	bool "8kB"
2144		- depends on CPU_R8000 \|\| CPU_CAVIUM_OCTEON
	2236	+ depends on CPU_CAVIUM_OCTEON
2145	2237	depends on !MIPS_VA_BITS_48
2146	2238	help
2147	2239	Using 8kB page size will result in higher performance kernel at
2148	2240	the price of higher memory consumption. This option is available
2149		- only on R8000 and cnMIPS processors. Note that you will need a
2150		- suitable Linux distribution to support this.
	2241	+ only on cnMIPS processors. Note that you will need a suitable Linux
	2242	+ distribution to support this.
2151	2243
2152	2244	config PAGE_SIZE_16KB
2153	2245	bool "16kB"
..	..	@@ -2187,7 +2279,7 @@
2187	2279	default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2188	2280	range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2189	2281	default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2190		- range 11 64
	2282	+ range 0 64
2191	2283	default "11"
2192	2284	help
2193	2285	The kernel memory allocator divides physically contiguous memory
..	..	@@ -2238,15 +2330,39 @@
2238	2330
2239	2331	config CPU_GENERIC_DUMP_TLB
2240	2332	bool
2241		- default y if !(CPU_R3000 \|\| CPU_R8000 \|\| CPU_TX39XX)
	2333	+ default y if !(CPU_R3000 \|\| CPU_TX39XX)
	2334	+
	2335	+config MIPS_FP_SUPPORT
	2336	+ bool "Floating Point support" if EXPERT
	2337	+ default y
	2338	+ help
	2339	+ Select y to include support for floating point in the kernel
	2340	+ including initialization of FPU hardware, FP context save & restore
	2341	+ and emulation of an FPU where necessary. Without this support any
	2342	+ userland program attempting to use floating point instructions will
	2343	+ receive a SIGILL.
	2344	+
	2345	+ If you know that your userland will not attempt to use floating point
	2346	+ instructions then you can say n here to shrink the kernel a little.
	2347	+
	2348	+ If unsure, say y.
	2349	+
	2350	+config CPU_R2300_FPU
	2351	+ bool
	2352	+ depends on MIPS_FP_SUPPORT
	2353	+ default y if CPU_R3000 \|\| CPU_TX39XX
	2354	+
	2355	+config CPU_R3K_TLB
	2356	+ bool
2242	2357
2243	2358	config CPU_R4K_FPU
2244	2359	bool
2245		- default y if !(CPU_R3000 \|\| CPU_TX39XX)
	2360	+ depends on MIPS_FP_SUPPORT
	2361	+ default y if !CPU_R2300_FPU
2246	2362
2247	2363	config CPU_R4K_CACHE_TLB
2248	2364	bool
2249		- default y if !(CPU_R3000 \|\| CPU_R8000 \|\| CPU_SB1 \|\| CPU_TX39XX \|\| CPU_CAVIUM_OCTEON)
	2365	+ default y if !(CPU_R3K_TLB \|\| CPU_SB1 \|\| CPU_CAVIUM_OCTEON)
2250	2366
2251	2367	config MIPS_MT_SMP
2252	2368	bool "MIPS MT SMP support (1 TC on each available VPE)"
..	..	@@ -2294,6 +2410,7 @@
2294	2410	config MIPSR2_TO_R6_EMULATOR
2295	2411	bool "MIPS R2-to-R6 emulator"
2296	2412	depends on CPU_MIPSR6
	2413	+ depends on MIPS_FP_SUPPORT
2297	2414	default y
2298	2415	help
2299	2416	Choose this option if you want to run non-R6 MIPS userland code.
..	..	@@ -2408,7 +2525,6 @@
2408	2525	depends on CPU_SB1 && CPU_SB1_PASS_2
2409	2526	default y
2410	2527
2411		-
2412	2528	choice
2413	2529	prompt "SmartMIPS or microMIPS ASE support"
2414	2530
..	..	@@ -2441,6 +2557,7 @@
2441	2557	config CPU_HAS_MSA
2442	2558	bool "Support for the MIPS SIMD Architecture"
2443	2559	depends on CPU_SUPPORTS_MSA
	2560	+ depends on MIPS_FP_SUPPORT
2444	2561	depends on 64BIT \|\| MIPS_O32_FP64_SUPPORT
2445	2562	help
2446	2563	MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
..	..	@@ -2459,8 +2576,23 @@
2459	2576	config XKS01
2460	2577	bool
2461	2578
	2579	+config CPU_HAS_DIEI
	2580	+ depends on !CPU_DIEI_BROKEN
	2581	+ bool
	2582	+
	2583	+config CPU_DIEI_BROKEN
	2584	+ bool
	2585	+
2462	2586	config CPU_HAS_RIXI
2463	2587	bool
	2588	+
	2589	+config CPU_NO_LOAD_STORE_LR
	2590	+ bool
	2591	+ help
	2592	+ CPU lacks support for unaligned load and store instructions:
	2593	+ LWL, LWR, SWL, SWR (Load/store word left/right).
	2594	+ LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
	2595	+ systems).
2464	2596
2465	2597	#
2466	2598	# Vectored interrupt mode is an R2 feature
..	..	@@ -2492,10 +2624,13 @@
2492	2624	config CPU_R4400_WORKAROUNDS
2493	2625	bool
2494	2626
	2627	+config CPU_R4X00_BUGS64
	2628	+ bool
	2629	+ default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
	2630	+
2495	2631	config MIPS_ASID_SHIFT
2496	2632	int
2497	2633	default 6 if CPU_R3000 \|\| CPU_TX39XX
2498		- default 4 if CPU_R8000
2499	2634	default 0
2500	2635
2501	2636	config MIPS_ASID_BITS
..	..	@@ -2508,6 +2643,76 @@
2508	2643	bool
2509	2644
2510	2645	config MIPS_CRC_SUPPORT
	2646	+ bool
	2647	+
	2648	+# R4600 erratum. Due to the lack of errata information the exact
	2649	+# technical details aren't known. I've experimentally found that disabling
	2650	+# interrupts during indexed I-cache flushes seems to be sufficient to deal
	2651	+# with the issue.
	2652	+config WAR_R4600_V1_INDEX_ICACHEOP
	2653	+ bool
	2654	+
	2655	+# Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
	2656	+#
	2657	+# 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
	2658	+# Hit_Invalidate_D and Create_Dirty_Excl_D should only be
	2659	+# executed if there is no other dcache activity. If the dcache is
	2660	+# accessed for another instruction immeidately preceding when these
	2661	+# cache instructions are executing, it is possible that the dcache
	2662	+# tag match outputs used by these cache instructions will be
	2663	+# incorrect. These cache instructions should be preceded by at least
	2664	+# four instructions that are not any kind of load or store
	2665	+# instruction.
	2666	+#
	2667	+# This is not allowed: lw
	2668	+# nop
	2669	+# nop
	2670	+# nop
	2671	+# cache Hit_Writeback_Invalidate_D
	2672	+#
	2673	+# This is allowed: lw
	2674	+# nop
	2675	+# nop
	2676	+# nop
	2677	+# nop
	2678	+# cache Hit_Writeback_Invalidate_D
	2679	+config WAR_R4600_V1_HIT_CACHEOP
	2680	+ bool
	2681	+
	2682	+# Writeback and invalidate the primary cache dcache before DMA.
	2683	+#
	2684	+# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
	2685	+# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
	2686	+# operate correctly if the internal data cache refill buffer is empty. These
	2687	+# CACHE instructions should be separated from any potential data cache miss
	2688	+# by a load instruction to an uncached address to empty the response buffer."
	2689	+# (Revision 2.0 device errata from IDT available on https://www.idt.com/
	2690	+# in .pdf format.)
	2691	+config WAR_R4600_V2_HIT_CACHEOP
	2692	+ bool
	2693	+
	2694	+# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
	2695	+# the line which this instruction itself exists, the following
	2696	+# operation is not guaranteed."
	2697	+#
	2698	+# Workaround: do two phase flushing for Index_Invalidate_I
	2699	+config WAR_TX49XX_ICACHE_INDEX_INV
	2700	+ bool
	2701	+
	2702	+# The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
	2703	+# opposes it being called that) where invalid instructions in the same
	2704	+# I-cache line worth of instructions being fetched may case spurious
	2705	+# exceptions.
	2706	+config WAR_ICACHE_REFILLS
	2707	+ bool
	2708	+
	2709	+# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
	2710	+# may cause ll / sc and lld / scd sequences to execute non-atomically.
	2711	+config WAR_R10000_LLSC
	2712	+ bool
	2713	+
	2714	+# 34K core erratum: "Problems Executing the TLBR Instruction"
	2715	+config WAR_MIPS34K_MISSED_ITLB
2511	2716	bool
2512	2717
2513	2718	#
..	..	@@ -2525,7 +2730,7 @@
2525	2730	#
2526	2731	config HIGHMEM
2527	2732	bool "High Memory Support"
2528		- depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA && !PREEMPT_RT_FULL
	2733	+ depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
2529	2734
2530	2735	config CPU_SUPPORTS_HIGHMEM
2531	2736	bool
..	..	@@ -2551,20 +2756,11 @@
2551	2756
2552	2757	config ARCH_FLATMEM_ENABLE
2553	2758	def_bool y
2554		- depends on !NUMA && !CPU_LOONGSON2
2555		-
2556		-config ARCH_DISCONTIGMEM_ENABLE
2557		- bool
2558		- default y if SGI_IP27
2559		- help
2560		- Say Y to support efficient handling of discontiguous physical memory,
2561		- for architectures which are either NUMA (Non-Uniform Memory Access)
2562		- or have huge holes in the physical address space for other reasons.
2563		- See <file:Documentation/vm/numa.rst> for more.
	2759	+ depends on !NUMA && !CPU_LOONGSON2EF
2564	2760
2565	2761	config ARCH_SPARSEMEM_ENABLE
2566	2762	bool
2567		- select SPARSEMEM_STATIC
	2763	+ select SPARSEMEM_STATIC if !SGI_IP27
2568	2764
2569	2765	config NUMA
2570	2766	bool "NUMA Support"
..	..	@@ -2573,15 +2769,27 @@
2573	2769	Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2574	2770	Access). This option improves performance on systems with more
2575	2771	than two nodes; on two node systems it is generally better to
2576		- leave it disabled; on single node systems disable this option
	2772	+ leave it disabled; on single node systems leave this option
2577	2773	disabled.
2578	2774
2579	2775	config SYS_SUPPORTS_NUMA
2580	2776	bool
2581	2777
	2778	+config HAVE_SETUP_PER_CPU_AREA
	2779	+ def_bool y
	2780	+ depends on NUMA
	2781	+
	2782	+config NEED_PER_CPU_EMBED_FIRST_CHUNK
	2783	+ def_bool y
	2784	+ depends on NUMA
	2785	+
2582	2786	config RELOCATABLE
2583	2787	bool "Relocatable kernel"
2584		- depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS32_R6 \|\| CPU_MIPS64_R6 \|\| CAVIUM_OCTEON_SOC)
	2788	+ depends on SYS_SUPPORTS_RELOCATABLE
	2789	+ depends on CPU_MIPS32_R2 \|\| CPU_MIPS64_R2 \|\| \
	2790	+ CPU_MIPS32_R5 \|\| CPU_MIPS64_R5 \|\| \
	2791	+ CPU_MIPS32_R6 \|\| CPU_MIPS64_R6 \|\| \
	2792	+ CPU_P5600 \|\| CAVIUM_OCTEON_SOC
2585	2793	help
2586	2794	This builds a kernel image that retains relocation information
2587	2795	so it can be loaded someplace besides the default 1MB.
..	..	@@ -2593,7 +2801,7 @@
2593	2801	depends on RELOCATABLE
2594	2802	range 0x0 0x01000000
2595	2803	default "0x00100000"
2596		- ---help---
	2804	+ help
2597	2805	A table of relocation data will be appended to the kernel binary
2598	2806	and parsed at boot to fix up the relocated kernel.
2599	2807
..	..	@@ -2607,17 +2815,17 @@
2607	2815	config RANDOMIZE_BASE
2608	2816	bool "Randomize the address of the kernel image"
2609	2817	depends on RELOCATABLE
2610		- ---help---
2611		- Randomizes the physical and virtual address at which the
2612		- kernel image is loaded, as a security feature that
2613		- deters exploit attempts relying on knowledge of the location
2614		- of kernel internals.
	2818	+ help
	2819	+ Randomizes the physical and virtual address at which the
	2820	+ kernel image is loaded, as a security feature that
	2821	+ deters exploit attempts relying on knowledge of the location
	2822	+ of kernel internals.
2615	2823
2616		- Entropy is generated using any coprocessor 0 registers available.
	2824	+ Entropy is generated using any coprocessor 0 registers available.
2617	2825
2618		- The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
	2826	+ The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2619	2827
2620		- If unsure, say N.
	2828	+ If unsure, say N.
2621	2829
2622	2830	config RANDOMIZE_BASE_MAX_OFFSET
2623	2831	hex "Maximum kASLR offset" if EXPERT
..	..	@@ -2625,7 +2833,7 @@
2625	2833	range 0x0 0x40000000 if EVA \|\| 64BIT
2626	2834	range 0x0 0x08000000
2627	2835	default "0x01000000"
2628		- ---help---
	2836	+ help
2629	2837	When kASLR is active, this provides the maximum offset that will
2630	2838	be applied to the kernel image. It should be set according to the
2631	2839	amount of physical RAM available in the target system minus
..	..	@@ -2641,11 +2849,22 @@
2641	2849
2642	2850	config HW_PERF_EVENTS
2643	2851	bool "Enable hardware performance counter support for perf events"
2644		- depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 \|\| CPU_MIPS64 \|\| CPU_R10000 \|\| CPU_SB1 \|\| CPU_CAVIUM_OCTEON \|\| CPU_XLP \|\| CPU_LOONGSON3)
	2852	+ depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 \|\| CPU_MIPS64 \|\| CPU_R10000 \|\| CPU_SB1 \|\| CPU_CAVIUM_OCTEON \|\| CPU_XLP \|\| CPU_LOONGSON64)
2645	2853	default y
2646	2854	help
2647	2855	Enable hardware performance counter support for perf events. If
2648	2856	disabled, perf events will use software events only.
	2857	+
	2858	+config DMI
	2859	+ bool "Enable DMI scanning"
	2860	+ depends on MACH_LOONGSON64
	2861	+ select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
	2862	+ default y
	2863	+ help
	2864	+ Enabled scanning of DMI to identify machine quirks. Say Y
	2865	+ here unless you have verified that your setup is not
	2866	+ affected by entries in the DMI blacklist. Required by PNP
	2867	+ BIOS code.
2649	2868
2650	2869	config SMP
2651	2870	bool "Multi-Processing support"
..	..	@@ -2665,7 +2884,7 @@
2665	2884	Y to "Enhanced Real Time Clock Support", below.
2666	2885
2667	2886	See also the SMP-HOWTO available at
2668		- <http://www.tldp.org/docs.html#howto>.
	2887	+ <https://www.tldp.org/docs.html#howto>.
2669	2888
2670	2889	If you don't know what to do here, say N.
2671	2890
..	..	@@ -2747,7 +2966,7 @@
2747	2966	prompt "Timer frequency"
2748	2967	default HZ_250
2749	2968	help
2750		- Allows the configuration of the timer frequency.
	2969	+ Allows the configuration of the timer frequency.
2751	2970
2752	2971	config HZ_24
2753	2972	bool "24 HZ" if SYS_SUPPORTS_24HZ \|\| SYS_SUPPORTS_ARBIT_HZ
..	..	@@ -2863,25 +3082,8 @@
2863	3082	specified in the "crashkernel=YM@XM" command line boot parameter
2864	3083	passed to the panic-ed kernel).
2865	3084
2866		-config SECCOMP
2867		- bool "Enable seccomp to safely compute untrusted bytecode"
2868		- depends on PROC_FS
2869		- default y
2870		- help
2871		- This kernel feature is useful for number crunching applications
2872		- that may need to compute untrusted bytecode during their
2873		- execution. By using pipes or other transports made available to
2874		- the process as file descriptors supporting the read/write
2875		- syscalls, it's possible to isolate those applications in
2876		- their own address space using seccomp. Once seccomp is
2877		- enabled via /proc/<pid>/seccomp, it cannot be disabled
2878		- and the task is only allowed to execute a few safe syscalls
2879		- defined by each seccomp mode.
2880		-
2881		- If unsure, say Y. Only embedded should say N here.
2882		-
2883	3085	config MIPS_O32_FP64_SUPPORT
2884		- bool "Support for O32 binaries using 64-bit FP"
	3086	+ bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2885	3087	depends on 32BIT \|\| MIPS32_O32
2886	3088	help
2887	3089	When this is enabled, the kernel will support use of 64-bit floating
..	..	@@ -2908,6 +3110,9 @@
2908	3110	select OF
2909	3111	select OF_EARLY_FLATTREE
2910	3112	select IRQ_DOMAIN
	3113	+
	3114	+config UHI_BOOT
	3115	+ bool
2911	3116
2912	3117	config BUILTIN_DTB
2913	3118	bool
..	..	@@ -2956,7 +3161,7 @@
2956	3161	choice
2957	3162	prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2958	3163	default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2959		- !MIPS_MALTA && \
	3164	+ !MACH_LOONGSON64 && !MIPS_MALTA && \
2960	3165	!CAVIUM_OCTEON_SOC
2961	3166	default MIPS_CMDLINE_FROM_BOOTLOADER
2962	3167
..	..	@@ -2986,10 +3191,6 @@
2986	3191	bool
2987	3192	default y
2988	3193
2989		-config HAVE_LATENCYTOP_SUPPORT
2990		- bool
2991		- default y
2992		-
2993	3194	config PGTABLE_LEVELS
2994	3195	int
2995	3196	default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
..	..	@@ -3001,47 +3202,14 @@
3001	3202
3002	3203	menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
3003	3204
3004		-config HW_HAS_EISA
3005		- bool
3006		-config HW_HAS_PCI
3007		- bool
3008		-
3009		-config PCI
3010		- bool "Support for PCI controller"
3011		- depends on HW_HAS_PCI
3012		- select PCI_DOMAINS
3013		- help
3014		- Find out whether you have a PCI motherboard. PCI is the name of a
3015		- bus system, i.e. the way the CPU talks to the other stuff inside
3016		- your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
3017		- say Y, otherwise N.
3018		-
3019		-config HT_PCI
3020		- bool "Support for HT-linked PCI"
3021		- default y
3022		- depends on CPU_LOONGSON3
3023		- select PCI
3024		- select PCI_DOMAINS
3025		- help
3026		- Loongson family machines use Hyper-Transport bus for inter-core
3027		- connection and device connection. The PCI bus is a subordinate
3028		- linked at HT. Choose Y for Loongson-3 based machines.
3029		-
3030		-config PCI_DOMAINS
3031		- bool
3032		-
3033		-config PCI_DOMAINS_GENERIC
3034		- bool
3035		-
3036	3205	config PCI_DRIVERS_GENERIC
3037		- select PCI_DOMAINS_GENERIC if PCI_DOMAINS
	3206	+ select PCI_DOMAINS_GENERIC if PCI
3038	3207	bool
3039	3208
3040	3209	config PCI_DRIVERS_LEGACY
3041	3210	def_bool !PCI_DRIVERS_GENERIC
3042	3211	select NO_GENERIC_PCI_IOPORT_MAP
3043		-
3044		-source "drivers/pci/Kconfig"
	3212	+ select PCI_DOMAINS if PCI
3045	3213
3046	3214	#
3047	3215	# ISA support is now enabled via select. Too many systems still have the one
..	..	@@ -3050,26 +3218,6 @@
3050	3218	#
3051	3219	config ISA
3052	3220	bool
3053		-
3054		-config EISA
3055		- bool "EISA support"
3056		- depends on HW_HAS_EISA
3057		- select ISA
3058		- select GENERIC_ISA_DMA
3059		- ---help---
3060		- The Extended Industry Standard Architecture (EISA) bus was
3061		- developed as an open alternative to the IBM MicroChannel bus.
3062		-
3063		- The EISA bus provided some of the features of the IBM MicroChannel
3064		- bus while maintaining backward compatibility with cards made for
3065		- the older ISA bus. The EISA bus saw limited use between 1988 and
3066		- 1995 when it was made obsolete by the PCI bus.
3067		-
3068		- Say Y here if you are building a kernel for an EISA-based machine.
3069		-
3070		- Otherwise, say N.
3071		-
3072		-source "drivers/eisa/Kconfig"
3073	3221
3074	3222	config TC
3075	3223	bool "TURBOchannel support"
..	..	@@ -3097,10 +3245,10 @@
3097	3245	default 15
3098	3246
3099	3247	config ARCH_MMAP_RND_COMPAT_BITS_MIN
3100		- default 8
	3248	+ default 8
3101	3249
3102	3250	config ARCH_MMAP_RND_COMPAT_BITS_MAX
3103		- default 15
	3251	+ default 15
3104	3252
3105	3253	config I8253
3106	3254	bool
..	..	@@ -3113,21 +3261,6 @@
3113	3261
3114	3262	config ZONE_DMA32
3115	3263	bool
3116		-
3117		-source "drivers/pcmcia/Kconfig"
3118		-
3119		-config HAS_RAPIDIO
3120		- bool
3121		- default n
3122		-
3123		-config RAPIDIO
3124		- tristate "RapidIO support"
3125		- depends on HAS_RAPIDIO \|\| PCI
3126		- help
3127		- If you say Y here, the kernel will include drivers and
3128		- infrastructure code to support RapidIO interconnect devices.
3129		-
3130		-source "drivers/rapidio/Kconfig"
3131	3264
3132	3265	endmenu
3133	3266
..	..	@@ -3207,3 +3340,5 @@
3207	3340	source "drivers/firmware/Kconfig"
3208	3341
3209	3342	source "arch/mips/kvm/Kconfig"
	3343	+
	3344	+source "arch/mips/vdso/Kconfig"