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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6

 kernel/arch/arm64/kernel/hw_breakpoint.c
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@@ -1,21 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
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  * using the CPU's debug registers.
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  *
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  * Copyright (C) 2012 ARM Limited
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  * Author: Will Deacon <will.deacon@arm.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #define pr_fmt(fmt) "hw-breakpoint: " fmt
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@@ -62,7 +51,7 @@
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 	case TYPE_DATA:
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 		return get_num_wrps();
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 	default:
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-		pr_warning("unknown slot type: %d\n", type);
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+		pr_warn("unknown slot type: %d\n", type);
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 		return 0;
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 	}
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 }
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@@ -123,7 +112,7 @@
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 	GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
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 	GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
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 	default:
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-		pr_warning("attempt to read from unknown breakpoint register %d\n", n);
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+		pr_warn("attempt to read from unknown breakpoint register %d\n", n);
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 	}
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 	return val;
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@@ -138,7 +127,7 @@
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 	GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
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 	GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
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 	default:
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-		pr_warning("attempt to write to unknown breakpoint register %d\n", n);
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+		pr_warn("attempt to write to unknown breakpoint register %d\n", n);
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 	}
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 	isb();
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 }
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@@ -156,7 +145,7 @@
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 	case AARCH64_BREAKPOINT_EL1:
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 		return DBG_ACTIVE_EL1;
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 	default:
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-		pr_warning("invalid breakpoint privilege level %d\n", privilege);
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+		pr_warn("invalid breakpoint privilege level %d\n", privilege);
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 		return -EINVAL;
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 	}
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 }
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@@ -268,7 +257,7 @@
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 		 * level.
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 		 */
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 		enable_debug_monitors(dbg_el);
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-		/* Fall through */
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+		fallthrough;
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 	case HW_BREAKPOINT_RESTORE:
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 		/* Setup the address register. */
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 		write_wb_reg(val_reg, i, info->address);
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@@ -551,10 +540,14 @@
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 			/* Allow halfword watchpoints and breakpoints. */
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 			if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
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 				break;
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+
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+			fallthrough;
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 		case 3:
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 			/* Allow single byte watchpoint. */
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 			if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
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 				break;
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+
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+			fallthrough;
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 		default:
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 			return -EINVAL;
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 		}
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@@ -661,7 +654,7 @@
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 		perf_bp_event(bp, regs);
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 		/* Do we need to handle the stepping? */
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-		if (is_default_overflow_handler(bp))
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+		if (uses_default_overflow_handler(bp))
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 			step = 1;
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 unlock:
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 		rcu_read_unlock();
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@@ -740,7 +733,7 @@
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 static int watchpoint_report(struct perf_event *wp, unsigned long addr,
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 			     struct pt_regs *regs)
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 {
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-	int step = is_default_overflow_handler(wp);
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+	int step = uses_default_overflow_handler(wp);
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 	struct arch_hw_breakpoint *info = counter_arch_bp(wp);
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 	info->trigger = addr;